Logic simulation and fault collapsing with shared structurally synthesized BDDs
author
Mironov, Dmitri
Ubar, Raimund-Johannes
Raik, Jaan
statement of authorship
Dmitri Mironov, Raimund Ubar, Jaan Raik
source
2014 19th IEEE European Test Symposium (ETS) : May 26th-30th, 2014, Paderborn, Germany : proceedings
location of publication
Piscataway
publisher
IEEE
year of publication
2014
pages
[2] p. : ill
conference name, date
19th IEEE European Test Symposium (ETS), May 26-30, 2014
conference location
Paderborn, Germany
subject term
integraallülitused
digitaalintegraallülitused
rikked
simulatsioon
keyword
digital circuits
logic models
shared structurally synthesized Binary Decision Diagrams
fault collapsing
logic simulation
ISBN
978-1-4799-3415-7
notes
Bibliogr.: 7 ref
TTÜ department
arvutitehnika instituut
language
inglise