Hierarchical timing-critical paths analysis in sequential circuits
author
Jürimägi, Lembit
Ubar, Raimund-Johannes
Jenihhin, Maksim
Raik, Jaan
Devadze, Sergei
Kostin, Sergei
statement of authorship
Lembit Jürimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin
source
2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain
publisher
IEEE
year of publication
2018
pages
6 p. : ill
conference name, date
28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018), 2 – 4 July 2018
conference location
Spain
url
https://doi.org/10.1109/PATMOS.2018.8464176
subject term
elektriahelad
järjendanalüüs
keyword
timing-critical path
gate-level analysis
BDDs
ISBN
978-1-5386-6365-3
978-1-5386-6366-0
notes
Bibliogr.: 17 ref
TalTech department
arvutisüsteemide instituut
language
inglise
Reserch Group
Centre for trustworthy and efficient computing hardware (TECH)
Centre of dependable computing systems