Rang, T., Tarnay, K., Mizsei, J. et al.

full record print

Silicon integrated circuit fabrication process modeling and simulation

author

Rang, Toomas

Tarnay, K.

Mizsei, Janos

statement of authorship

T. Rang, K. Tarnay, J. Mizsei, P. Baji, B. Kovacs, G. Drozdy

source

Periodica polytechnica. Electrical engineering = Электротехника

publisher

Akademiai Kiado

journal volume number month

vol. 24, no. 1-2

year of publication

1980

pages

p. 109-113

url

https://www.ester.ee/record=b1198855*est

ISSN

0324-6000

language

inglise

Märksõnad ja võtmesõnad

subject term

pooljuhtide tehnoloogia

integraallülitused

TalTechi üksused

TalTech department

elektroonika kateeder

Rang, T., Tarnay, K., Mizsei, J. et al. Silicon integrated circuit fabrication process modeling and simulation // Periodica polytechnica. Electrical engineering = Электротехника (1980) vol. 24, no. 1-2, p. 109-113. https://www.ester.ee/record=b1198855*est