Translating Common Security Assertions Across Processor Designs : A RISC-V Case Study
author
Imtiaz, Sharjeel
Reinsalu, Uljana
Ghasempouri, Tara
statement of authorship
Sharjeel Imtiaz, Uljana Reinsalu, Tara Ghasempouri
source
2025 IEEE International Symposium on Circuits and Systems (ISCAS)
publisher
IEEE
year of publication
2025
pages
5 p
conference name, date
IEEE International Symposium on Circuits and Systems (ISCAS), 25-28 May 2025
conference location
London, United Kingdom
url
https://doi.org/10.1109/ISCAS56072.2025.11043977
subject term
turvalisus
protsessorid
pahavara
keyword
Security Verification
Security Assertion
RISC-V Processor
Hardware Trojan
Register-Transfer Level (RTL)
ISSN
2158-1525
ISBN
9798350356830
scientific publication
teaduspublikatsioon
classifier
3.1
TalTech department
Department of Computer Systems
Arvutisüsteemide instituut
language
Estonian,English
Eesti,Inglise