An Accelerator-based architecture utilizing an efficient memory link for modern computational requirements
author
statement of authorship
Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi
source
2019 IEEE East-West Design & Test Symposium (EWDTS)
location of publication
[S.l.]
publisher
year of publication
pages
6 p. : ill
conference name, date
2019 IEEE East-West Design & Test Symposium (EWDTS), 13-16 Sept. 2019
conference location
Batumi, Georgia
subject term
keyword
accelerator-based architecture
on-chip communication architectures
ISSN
2472-761X
2373-826X
ISBN
978-1-7281-1003-5
978-1-7281-1004-2
notes
Bibliogr.: 11 ref
TTÜ department
language
inglise
Yousefzadeh, S., Basharkhah, K., Raik, J., Jenihhin, M. et al. An Accelerator-based architecture utilizing an efficient memory link for modern computational requirements // 2019 IEEE East-West Design & Test Symposium (EWDTS). [S.l.] : IEEE, 2019. 6 p. : ill.