Puttaswamy, K., Choi, K.-W., Park, J.C., Mooney III, V.J., Chatterjee, A., Ellervee, P.

full record print

System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory

author

Puttaswamy, Kiran

Choi, Kyu-Won

Park, Jun Cheol

Mooney III, Vincent J.

Chatterjee, Abhijit

Ellervee, Peeter

statement of authorship

Kiran Puttaswamy, Kyu-Won Choi, Jun Cheol Park, Vincent J.Mooney III, Abhijit Chatterjee and Peeter Ellervee

source

ISSS'02, October 2-4, 2002, Kyoto, Japan

year of publication

2002

pages

p. 225-230 : ill

url

https://ieeexplore.ieee.org/document/1227182

notes

Bibliogr.: 20 ref

language

inglise

Märksõnad ja võtmesõnad

subject term

manussüsteemid

integraallülitused

projekteerimine

optimeerimine

Puttaswamy, K., Choi, K.-W., Park, J.C., Mooney III, V.J., Chatterjee, A., Ellervee, P. System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory // ISSS'02, October 2-4, 2002, Kyoto, Japan., 2002. p. 225-230 : ill. https://ieeexplore.ieee.org/document/1227182