Hierarchical defect level test quality analysisBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesVILAB User Forum2000 / [11] p

Hierarchical test generation for digital circuits represented by Decision Diagrams : thesis on informatics and system engineeringRaik, Jaan2001 https://www.ester.ee/record=b1578107*est

Lihtsad veebisaitide testimisvahendidTepandi, Jaak; Tepandi, LiisiA & A2000 / 4, lk. 14-21 https://artiklid.elnet.ee/record=b1004807*est

Piecewise linearly approximated sine wave for dynamic quality tests of A/D convertersLand, RaulProceedings of the Estonian Academy of Sciences. Engineering2000 / 2, p. 113-119 : ill https://artiklid.elnet.ee/record=b1004041*est

Tarkvara kvaliteet ja standardidTepandi, Jaak1999 https://www.ester.ee/record=b1331246*est

Testability analysis for efficient register-transfer level test generation [Electronic resource]Nõmmeots, Tanel; Raik, Jaan; Ubar, Raimund-Johannes9th International Conference MIXDES 2002 : Mixed Design of Integrated Circuits and Systems, Wroclaw, Poland, 20-22 June 20022002 / [4] p. [CD-ROM]

Testability calculation for digital circuits with decision diagramsUbar, Raimund-Johannes3rd IEEE Latin American Test Workshop : LATW'02, Montevideu, Uruguay, February 10-13, 2002 : digest of papers2002 / p. 137-143 : ill https://dblp.org/rec/conf/latw/Ubar02.html

Testability guided hierarchical test generation with decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Nõmmeots, Tanel20th IEEE NORCHIP Conference : Copenhagen, Denmark, November 11-12, 20022002 / p. 265-271 https://www.semanticscholar.org/paper/Testability-Guided-Hierarchical-Test-Generation-Ubar-Raik/c6301ac35d003c92f3867f26e2e75b87e1ad9b47