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Automated design error localization in RTL designsJenihhin, Maksim; Tšepurov, Anton; Tihhomirov, Valentin; Raik, Jaan; Hantson, Hanno; Ubar, Raimund-Johannes; Bartsch, Günter; Meza Escobar, Jorge Hernan; Wuttke, Heinz-DietrichIEEE design & test of computers2014 / p. 83-92 : ill https://doi.org/10.1109/MDAT.2013.2271420 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Automated identification of application-dependent safe faults in automotive systems-on-a-chipsBagbaba, Ahmet Cagri; Augusto da Silva, Felipe; Sonza Reorda, Matteo; Hamdioui, Said; Jenihhin, Maksim; Sauer, ChristianElectronics2022 / art. 319 https://doi.org/10.3390/electronics11030319 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Automatic SoC level test path synthesis based on partial functional modelsTšertov, Anton; Ubar, Raimund-Johannes; Jutman, Artur; Devadze, Sergei2011 Asian Test Symposium (ATS) : New Delhi, India2011 / p. 532-538 https://ieeexplore.ieee.org/document/6114730

Benchmarking advanced security closure of physical layoutsEslami, Mohammad; Knechtel, Johann; Sinanoglu, Ozgur; Karri, Ramesh; Pagliarini, Samuel NascimentoISPD '23 : proceedings of the 2023 International Symposium on Physical Design2023 / p. 256-264 https://doi.org/10.1145/3569052.3578924 https://dl.acm.org/doi/pdf/10.1145/3569052.3578924

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Capacitance-to-digital: A single chip detector for capillary electrophoresisDrevinskas, Tomas; Kaljurand, Mihkel; Maruška, AudriusElectrophoresis2014 / p. 2401-2407 : ill https://doi.org/10.1002/elps.201300468 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Chip-to-Chip authentication method based on SRAM PUF and public key cryptographyKarageorgos, Ioannis; Isgenc, Mehmet Meric; Pagliarini, Samuel Nascimento; Pileggi, LarryJournal of hardware and systems security2019 / p. 382–396 : ill https://doi.org/10.1007/s41635-019-00080-y

Circuit simulation program oriented physical modeling of integrated circuit elementsRang, Toomas; Tarnay, K.; Szekely, V.Periodica polytechnica. Electrical engineering = Электротехника1980 / p. 37-45 https://www.ester.ee/record=b1198855*est

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Compact avalanche transistor model for circuit simulation of Bi and BiCMOS cellsBubennikov, Alexander N.; Kobosev, Gennady; Kozhuhov, D.; Uchenov, A.BEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia). 21994 / p. 523-527: ill https://www.ester.ee/record=b2150914*est

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Decision diagrams - from a mathematical notion to engineering applicationsStankovic, Radomir S.; Ubar, Raimund-Johannes; Astola, JaakkoFacta Universitatis [Niš]. Series electronics and energetics2011 / p. 281-301 : ill http://dx.doi.org/10.2298/FUEE1103281S

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DefSim: measurement environment for CMOS defectsBorejko, Tomasz; Jutman, Artur; Pleskacz, Witold A.; Ubar, Raimund-Johannes2006 25th International Conference on Microelectronics : Belgrade, Serbia and Montenegro, 14-17 May 2006 : proceedings. Volume 22006 / p. 679-682 https://ieeexplore.ieee.org/document/1651048

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Synthesis of multiple fault oriented test groups from single fault test sets [Electronic resource]Ubar, Raimund-Johannes; Kostin, Sergei; Raik, Jaan2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) : 26-28 March 2013, Abu Dhabi, UAE2013 / p. 36-41 : ill [CD-ROM]

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Test cost minimization for hybrid BISTJervan, Gert; Peng, Zebo; Ubar, Raimund-JohannesIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 25-27 October 2000, Yamanashi, Japan : proceedings2000 / p. 283-298 : ill https://ieeexplore.ieee.org/abstract/document/887168

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