• An Accelerator-based architecture utilizing an efficient memory link for modern computational requirementsYousefzadeh, Saba; Basharkhah, Katayoon; Raik, Jaan; Jenihhin, Maksim2019 IEEE East-West Design & Test Symposium (EWDTS)2019 / 6 p. : ill https://doi.org/10.1109/EWDTS.2019.8884481
• An efficient analog convolutional neural network hardware accelerator enabled by a novel memoryless architecture for insect-sized robotsDadras, Iman; Ahmadilivani, Mohammad Hasan; Banerji, Saoni; Raik, Jaan; Abloo, Alvo2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST) : Bremen, Germany : 08-10 June 20222022 / p. 1-6 https://doi.org/10.1109/MOCAST54814.2022.9837551
• Elliptic-curve crypto processor for RFID applicationsRashid, Muhammad; Jamal, Sajjad Shaukat; Khan, Sikandar Zulqarnain; Alharbi, Adel R.; Aljaedi, Amer; Imran, MalikApplied Sciences (Switzerland)2021 / art. 7079 https://doi.org/10.3390/app11157079 https://www.scopus.com/sourceid/21100829268 https://www.scopus.com/record/display.uri?eid=2-s2.0-85112666228&origin=resultslist&sort=plf-f&src=s&sid=c5fbe1d759bf21282dc69b96619c9ecf&sot=b&sdt=b&s=DOI%2810.3390%2Fapp11157079%29&sl=31&sessionSearchId=c5fbe1d759bf21282dc69b96619c9ecf&relpos=0 https://jcr.clarivate.com/jcr-jp/journal-profile?journal=APPL%20SCI-BASEL&year=2022 https://www.webofscience.com/wos/woscc/full-record/WOS:000681948400001
• Fully-fusible convolutional neural networks for end-to-end fused architecture with FPGA implementationDadras, Iman; Seydi, Sakineh; Ahmadilivani, Mohammad Hasan; Raik, Jaan; Salehi, Mostafa E.2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)2023 / 5 p. https://doi.org/10.1109/ICECS58634.2023.10382831
• Hardware accelerators for information retrieval and data miningSklyarov, Valery; Skliarova, Iouliia; Silva, João; Sudnitsõn, Aleksander; Rjabov, Artjom2015 International Conference on Information and Communication Technology Research (ICTRC2015) : Abu Dhabi, United Arab Emirates, May 17-19, 20152015 / p. 202-205 : ill http://dx.doi.org/10.1109/ICTRC.2015.7156457
• Heterogeneous Approximation of DNN HW Accelerators based on Channels VulnerabilityCherezova, Natalia; Pappalardo, Salvatore; Taheri, Mahdi; Ahmadilivani, Mohammad Hasan; Deveautour, Bastien; Bosio, Alberto; Raik, Jaan; Jenihhin, Maksim2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration (VLSI-SoC)2024 / 4 p. : ill https://doi.org//10.1109/VLSI-SoC62099.2024.10767798
• High-speed design of postquantum cryptography with optimized hashing and multiplicationImran, Malik; Aikata, Aikata; Roy, Sujoy Sinha; Pagliarini, Samuel NascimentoIEEE Transactions on Circuits and Systems II : Express Briefs2023 / p. 847-851 : ill https://doi.org//10.1109/TCSII.2023.3273821
• SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN AcceleratorsTaheri, Mahdi; Daneshtalab, Masoud; Raik, Jaan; Jenihhin, Maksim; Pappalardo, Salvatore; Jimenez, Paul; Deveautour, Bastien; Bosio, Alberto2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS) : 03-05 April 2024, Kielce, Poland2024 / p. 19–24 : ill https://doi.org//10.1109/DDECS60919.2024.10508925