• Assembling low-level tests to high-level symbolic test framesJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings [of the] 15th NORCHIP Conference, Tallinn, 10-11 November 19971997 / p. 275-280: ill
• Automatic test generation system for VLSIJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the First Electronic Circuits and Systems Conference : Bratislava, Slovakia, September 4-5, 19971997 / p. 255-258
• CAD software for digital test and diagnosticsJervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesProceedings of International Conference on Design and Diagnostics of Electronic Circuits and Systems, Ostrava, Czech Republik, May 12-14, 19971997 / p. 35-40
• DECIDER : a decision diagram based hierarchical test generation systemJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 2nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Szczyrk, Poland, September 2-4, 19981998 / p. 269-273 https://www.ida.liu.se/labs/eslab/publications/pap/db/DDECS98.pdf
• A decision diagram based hierarchical test pattern generatorJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesBEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 159-162: ill
• Fast and efficient static compaction of test sequences using bipartite graph representationsMarkus, Antti; Raik, Jaan; Ubar, Raimund-JohannesECS'99 : proceedings of the 2nd Electronic Circuits and Systems Conference : September 6-8, 1999, Bratislava, Slovakia1999 / p. 17-20
• Fault model and test synthesis for RISC-processorsUbar, Raimund-Johannes; Markus, Antti; Jervan, Gert; Raik, JaanBEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 229-232: ill
• A hierarchical automatic test pattern generator based on using alternative graphsBrik, Marina; Jervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 4th International Workshop Mixed Design of Integrated Circuits and Systems : MIXDES'97 : Poznan, Poland, 12-14 June 19971997 / p. 415-420
• Hierarchical test generation for digital systemsBrik, Marina; Jervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesMixed design of integrated circuits and systems1998 / p. 131-136: ill https://link.springer.com/chapter/10.1007/978-1-4615-5651-0_20
• Hierarchical test generation with multi-level decision diagram modelsJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 7th IEEE North Atlantic Test Workshop, West Greenwich RI, USA, May 28-29, 19981998 / p. 26-33 https://www.academia.edu/67811738/Hierarchical_Test_Generation_with_Multi_Level_Decision_Diagram_Models?hb-g-sw=7883185
• Low-cost CAD system for teaching digital testUbar, Raimund-Johannes; Raik, Jaan; Paomets, Priidu; Ivask, Eero; Jervan, Gert; Markus, AnttiMicroelectronics education : proceedings of the European Workshop, Grenoble, France, 5-6 Feb 19961996 / p. 185-188
• Mixed-level deterministic-random test generation for digital systemsJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 19981998 / p. 335-340
• Mixed-level test generator for digital systemsBrik, Marina; Jervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering1997 / 4, p. 271-282 : ill
• A set of tools for estimating quality of built-in self-test in digital circuitsJervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the International Symposium on Signals, Circuits and Systems, Iasi (Romania), October 2-3, 19971997 / p. 362-365
• Teaching test and design for testability with TURBO-TESTER softwareJervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 3rd Workshop on Mixed Design of Integrated Circuits and Systems, Lodz, May 19961996 / p. 589-594
• Test set minimization using bipartite graphsMarkus, Antti; Raik, Jaan; Ubar, Raimund-JohannesBEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 175-178: ill
• Turbo tester : a CAD system for teaching digital testJervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesMicroelectronics education : proceedings of the 2nd European Workshop held in Noordwijkerhout, The Netherlands, 14-15 May 19981998 / p. 287-290: ill https://link.springer.com/chapter/10.1007/978-94-011-5110-8_66
• VHDL based test generation systemJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 5th Electronic Devices and Systems Conference, Brno, June 11-12, 19981998 / p. 145-148