• An area aware accelerator for elliptic curve point multiplicationImran, Malik; Pagliarini, Samuel Nascimento; Rashid, Muhammad Haroon27th IEEE International Conference on Electronics Circuits and Systems, (ICECS) 2020, Glasgow, UK, Virtual Conference, November 23-25, 2020 : proceedings2020 / 4 p https://doi.org/10.1109/ICECS49266.2020.9294908
• Benchmarking advanced security closure of physical layoutsEslami, Mohammad; Knechtel, Johann; Sinanoglu, Ozgur; Karri, Ramesh; Pagliarini, Samuel NascimentoISPD '23 : proceedings of the 2023 International Symposium on Physical Design2023 / p. 256-264 https://doi.org/10.1145/3569052.3578924 https://dl.acm.org/doi/pdf/10.1145/3569052.3578924
• CAC 2.0 : a corrupt and correct logic locking technique resilient to structural analysis attacksAksoy, Levent; Yasin, Muhammad; Pagliarini, Samuel NascimentoarXiv.org2024 / 6 p. : ill https://doi.org/10.48550/arXiv.2401.07142
• Chip-to-Chip authentication method based on SRAM PUF and public key cryptographyKarageorgos, Ioannis; Isgenc, Mehmet Meric; Pagliarini, Samuel Nascimento; Pileggi, LarryJournal of hardware and systems security2019 / p. 382–396 : ill https://doi.org/10.1007/s41635-019-00080-y
• Design obfuscation versus testFarahmandi, Farimah; Sinanoglu, Ozgur; Blanton, Ronald; Pagliarini, Samuel Nascimento2020 IEEE European Test Symposium (ETS) : ETS 2020, May 25 - 29, 2020, Tallinn, Estonia2020 / 10 p https://doi.org/10.1109/ETS48528.2020.9131590
• Design space exploration of SABER in 65nm ASICImran, Malik; Almeida, Felipe; Raik, Jaan; Basso, Andrea; Roy, Sujoy Sinha; Pagliarini, Samuel NascimentoASHES '21 : proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security2021 / p. 85-90 https://doi.org/10.1145/3474376.3487278
• Evaluating architectural, redundancy, and implementation strategies for radiation hardening of FinFET integrated circuitsPagliarini, Samuel Nascimento; Benites, Luis; Martins, Mayler; Rech, Paolo; Kastensmidt, FernandaIEEE transactions on nuclear science2021 / p. 1045-1053 https://doi.org/10.1109/TNS.2021.3070643 https://www.scopus.com/sourceid/17368 https://www.scopus.com/record/display.uri?eid=2-s2.0-85103797089&origin=inward&txGid=6c92c2fbb6cf4232257945f91e1079ba https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20T%20NUCL%20SCI&year=2022 https://www.webofscience.com/wos/woscc/full-record/WOS:000655537500073
• An experimental study of building blocks of lattice-based NIST post-quantum cryptographic algorithmsImran, Malik; Abideen, Zain Ul; Pagliarini, Samuel NascimentoElectronics2020 / art. 1953, 26 p. : ill https://doi.org/10.3390/electronics9111953 https://www.scopus.com/sourceid/21100829272 https://www.scopus.com/record/display.uri?eid=2-s2.0-85096516874&origin=inward&txGid=8ae2f54b5d9b18229c39260c95bb0b68 https://jcr.clarivate.com/jcr-jp/journal-profile?journal=ELECTRONICS-SWITZ&year=2022 https://www.webofscience.com/wos/woscc/full-record/WOS:000593628700001
• From FPGAs to obfuscated eASICs : design and security trade-offsAbideen, Zain Ul; Perez, Tiago Diadami; Pagliarini, Samuel NascimentoIEEE Asian Hardware-Oriented Security and Trust (AsianHOST)2021 / p. 1-4 https://doi.org/10.1109/AsianHOST53231.2021.9699758
• From virtual characterization to test-chips : DFM analysis through pattern enumerationMartins, Mayler G.A.; Pagliarini, Samuel Nascimento; Isgenc, Mehmet Meric; Pileggi, LarryIEEE transactions on computer-aided design of integrated circuits and systems2020 / p. 520-532 https://doi.org//10.1109/TCAD.2018.2889772
• G-GPU : a fully-automated generator of GPU-like ASIC acceleratorsPerez, Tiago Diadami; Gonçalves, Marcio M.; Gobatto, Leonardo; Brandalero, Marcelo; Azambuja, Jose Rodrigo; Pagliarini, Samuel Nascimento2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) : 14-23 March 2022 : Antwerp, Belgium2022 / p. 544 - 547 https://doi.org/10.23919/DATE54114.2022.9774758
• Hardware obfuscation of digital FIR filtersAksoy, Levent; Hepp, Alexander; Baehr, Johanna; Pagliarini, Samuel Nascimento2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) : Prague, Czech Republic : April 6-8, 2022 : proceedings2022 / p. 68-73 https://doi.org/10.48550/arXiv.2202.10022 https://doi.org/10.1109/DDECS54261.2022.9770141
• Hardware realization of lattice-based post-quantum cryptography = Võrel põhinev post-kvant-krüptograafia riistvaraline realisatsioonImran, Malik2023 https://www.ester.ee/record=b5571216*est https://doi.org/10.23658/taltech.33/2023 https://digikogu.taltech.ee/et/Item/75aeb070-cb8b-4511-beaf-cbea3fca147d https://www.ester.ee/record=b5571216*est
• Hardware trojan insertion in finalized layouts : from methodology to a silicon demonstrationPerez, Tiago Diadami; Pagliarini, Samuel NascimentoIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2023 / p. 2094-2107 https://doi.org/10.1109/TCAD.2022.3223846 https://www.scopus.com/sourceid/27724 https://www.scopus.com/record/display.uri?eid=2-s2.0-85144011739&origin=resultslist&sort=plf-f&src=s&sid=f6bea21f940b112407e8b3b930cd5a56&sot=b&sdt=b&s=DOI%2810.1109%2FTCAD.2022.3223846%29&sl=141&sessionSearchId=f6bea21f940b112407e8b3b930cd5a56 https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20T%20COMPUT%20AID%20D&year=2022 https://www.webofscience.com/wos/woscc/full-record/WOS:001017411600002
• Hardware Trojans for confidence reduction and misclassifications on neural networksGrailoo, Mahdieh; Leier, Mairo; Pagliarini, Samuel NascimentoProceedings Of The Twenty Third International Symposium On Quality Electronic Design (ISQED 2022)2022 / art. 180541, p. 230-235 https://doi.org/10.1109/ISQED54688.2022.9806246
• High-level intellectual property obfuscation via decoy constantsAksoy, Levent; Nguyen, Quang-Linh; Almeida, Felipe; Raik, Jaan; Flottes, Marie-Lise; Dupuis, Sophie; Pagliarini, Samuel Nascimento2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) : Torino, Italy, 28-30 June 20212021 / p. 1-7 https://doi.org/10.1109/IOLTS52814.2021.9486714
• High-speed design of postquantum cryptography with optimized hashing and multiplicationImran, Malik; Aikata, Aikata; Roy, Sujoy Sinha; Pagliarini, Samuel NascimentoIEEE Transactions on Circuits and Systems II : Express Briefs2023 / p. 847-851 : ill https://doi.org//10.1109/TCSII.2023.3273821
• High-speed SABER key encapsulation mechanism in 65nm CMOSImran, Malik; Almeida, Felipe; Basso, Andrea; Roy, Sujoy Sinha; Pagliarini, Samuel NascimentoJournal of cryptographic engineering2023 / p. 461-471 : ill https://doi.org/10.1007/s13389-023-00316-2 https://www.scopus.com/sourceid/21100266502 https://www.scopus.com/record/display.uri?eid=2-s2.0-85151318828&origin=inward&txGid=9cfbc0e899663ad56e41cb0759f4e969 https://jcr.clarivate.com/jcr-jp/journal-profile?journal=J%20CRYPTOGR%20ENG&year=2023 https://www.webofscience.com/wos/woscc/full-record/WOS:000960662600001
• Hybrid protection of digital FIR filtersAksoy, Levent; Nguyen, Quang-Linh; Almeida, Felipe; Raik, Jaan; Flottes, Marie-Lise; Dupuis, Sophie; Pagliarini, Samuel NascimentoIEEE transactions on Very Large Scale Integration (VLSI) Systems2023 / p. 812-825 : ill https://doi.org/10.1109/TVLSI.2023.3253641 https://www.scopus.com/sourceid/12300 https://www.scopus.com/record/display.uri?eid=2-s2.0-85151356738&origin=inward&txGid=2cbf13db49fa5db5d3e09767a51c47df https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20T%20VLSI%20SYST&year=2023 https://www.webofscience.com/wos/woscc/full-record/WOS:000953458300001
• Impact of orientation on the bias of SRAM-based PUFsAbideen, Zain Ul; Wang, Rui; Perez, Tiago Diadami; Schrijen, Geert-Jan; Pagliarini, Samuel NascimentoarXiv.org2023 / 7 p. : ill https://doi.org/10.48550/arXiv.2308.06730
• Impact of orientation on the bias of SRAM-based PUFsAbideen, Zain Ul; Wang, Rui; Perez, Tiago Diadami; Schrijen, Geert-Jan; Pagliarini, Samuel NascimentoIEEE design & test2024 / p. 14-20 https://doi.org/10.1109/MDAT.2023.3322621
• KaLi: a crystal for post-quantum security using kyber and dilithiumAikata, Aikata; Mert, Ahmet Can; Imran, Malik; Pagliarini, Samuel Nascimento; Roy, Sujoy SinhaIEEE Transactions on Circuits and Systems I : regular papers2023 / p. 747–758 https://doi.org/10.1109/TCSI.2022.3219555 https://www.scopus.com/sourceid/11000153733 https://www.scopus.com/record/display.uri?eid=2-s2.0-85141557756&origin=inward&txGid=727a21b83d3f6f1b6f8d417e593c52c4 https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20T%20CIRCUITS-I&year=2023 https://www.webofscience.com/wos/woscc/full-record/WOS:000886850400001
• KRATT : QBF-assisted removal and structural analysis attack against logic lockingAksoy, Levent; Yasin, Muhammad; Pagliarini, Samuel NascimentoarXiv.org2023 / 7 p. : ill https://doi.org/10.48550/arXiv.2311.05982
• Latch-Based logic lockingSweeney, J.; Mohammed Zackriya, V.; Pagliarini, Samuel Nascimento; Pileggi, LarryProceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, HOST 20202020 / p. 132−141 : ill https://doi.org/10.1109/HOST45689.2020.9300256
• Latest trends in hardware security and privacyDi Natale, Giorgio; Regazzoni, Francesco; Albanese, Vincent; Lhermet, Frank; Loisel, Yann; Sensaoui, Abderrahmane; Pagliarini, Samuel Nascimento33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : ESA-ESRIN, Italy (On-line Virtual Event),October 19–21, 20202020 / 4 p. : ill https://doi.org/10.1109/DFT50435.2020.9250816
• Leveraging FPGA Reconfigurability as an Obfuscation Asset = FPGA ümberkonfigureeritavuse rakendamine hägustamise vahendinaAbideen, Zain Ul2024 https://digikogu.taltech.ee/et/Item/660d923b-44d2-4993-898f-324ab2088199 https://www.ester.ee/record=b5649944*est https://doi.org/10.23658/taltech.1/2024
• Leveraging layout-based effects for locking analog ICsAljafar, Muayad J.; Azais, Florence; Flottes, Marie-Lise; Pagliarini, Samuel NascimentoASHES'22: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security2022 / p. 5-13 https://doi.org/10.1145/3560834.3563826
• Logic IP for low-cost IC design in advanced CMOS nodesIsgenc, Mehmet Meric; Martins, Mayler G.A.; Zackriya, V. Mohammed; Pagliarini, Samuel Nascimento; Pileggi, LarryIEEE Transactions on Very Large Scale Integration (VLSI) Systems2020 / p. 585-595 https://doi.org//10.1109/TVLSI.2019.2942825
• Multiplierless design of high-speed very large constant multiplicationsAksoy, Levent; Roy, Debapriya Basu; Imran, Malik; Pagliarini, Samuel Nascimento2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC 2024)2024 / p. 957-962 https://doi.org/10.1109/ASP-DAC58780.2024.10473954
• Multiplierless design of very large constant multiplications in cryptographyAksoy, Levent; Roy, Debapriya Basu; Imran, Malik; Karl, Patrick; Pagliarini, Samuel NascimentoIEEE Transactions on Circuits and Systems II : Express Briefs2022 / p. 4503-4507 https://doi.org/10.1109/TCSII.2022.3191662 https://www.scopus.com/sourceid/9500153930 https://www.scopus.com/record/display.uri?eid=2-s2.0-85135215139&origin=inward&txGid=f23b49ab5b48f3a0ef3f5de7101fab80 https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20T%20CIRCUITS-II&year=2022 https://www.webofscience.com/wos/woscc/full-record/WOS:000875902500066
• Obfuscating the hierarchy of a digital IPBasiashvili, Giorgi; Abideen, Zain Ul; Pagliarini, Samuel NascimentoEmbedded Computer Systems : Architectures, Modeling, and Simulation :22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022 : proceedings2022 / p. 303-314 https://doi.org/10.1007/978-3-031-15074-6_28 https://www.scopus.com/sourceid/25674 https://www.scopus.com/record/display.uri?eid=2-s2.0-85136925059&origin=inward&txGid=23ee61f4e0efc518acc13a0119588a60 https://jcr.clarivate.com/jcr-jp/journal-profile?journal=LECT%20NOTES%20ARTIF%20INT&year=2005 https://www.webofscience.com/wos/woscc/full-record/WOS:000874744300019
• On the use of defensive schemes for hardware security = Kaitseskeemid riistvara turvalisuse tagamiseksEslami, Mohammad2024 https://www.ester.ee/record=b5701420*est https://doi.org/10.23658/taltech.53/2024 https://digikogu.taltech.ee/et/Item/068530be-4810-4489-9604-fb838d298b45
• An open-source library of large integer polynomial multipliersImran, Malik; Abideen, Zain Ul; Pagliarini, Samuel Nascimento24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, Austria, April 7-9 20212021 / p. 145-150 : ill https://doi.org/10.1109/DDECS52668.2021.9417065
• An overview of FPGA-inspired obfuscation techniquesAbideen, Zain Ul; Gokulanathan, Sumathi; Aljafar, Muayad J.; Pagliarini, Samuel NascimentoarXiv.org2023 / 30 p. : ill https://doi.org/10.48550/arXiv.2305.15999
• A pragmatic methodology for blind hardware trojan insertion in finalized layoutsHepp, Alexander; Perez, Tiago Diadami; Pagliarini, Samuel Nascimento; Sigl, GeorgICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design2022 / art. 69, p. 1-9 : ill https://doi.org/10.1145/3508352.3549452 https://www.scopus.com/sourceid/51882 https://www.scopus.com/record/display.uri?eid=2-s2.0-85137785373&origin=inward&txGid=b339c373005c47ea7212f2cc0bbbf3de https://www.webofscience.com/wos/woscc/full-record/WOS:000981574300068
• Preventing distillation-based attacks on Neural Network IPGrailoo, Mahdieh; Abideen, Zain Ul; Leier, Mairo; Pagliarini, Samuel NascimentoarXiv.org2022 / 7 p. : ill https://doi.org/10.48550/arXiv.2204.00292
• A probabilistic synapse with strained MTJs for Spiking Neural NetworksPagliarini, Samuel Nascimento; Bhuin, Sudipta; Isgenc, Mehmet Meric; Biswas, Ayan Kumar; Pileggi, LarryIEEE Transactions on Neural Networks and Learning Systems2020 / p. 1113-1123 : ill https://doi.org/10.1109/TNNLS.2019.2917819
• Ransomware attack as Hardware Trojan : a feasibility and demonstration studyAlmeida, Felipe; Imran, Malik; Raik, Jaan; Pagliarini, Samuel NascimentoIEEE Access2022 / p. 44827-44839 https://doi.org/10.1109/ACCESS.2022.3168991 https://www.scopus.com/sourceid/21100374601 https://www.scopus.com/record/display.uri?eid=2-s2.0-85129163754&origin=inward&txGid=16e190db632af5d9830eb3f60cff1f2b https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20ACCESS&year=2022 https://www.webofscience.com/wos/woscc/full-record/WOS:000790727000001
• Resynthesis-based attacks against logic lockingAlmeida, Felipe; Aksoy, Levent; Nguyen, Quang-Linh; Dupuis, Sophie; Flottes, Marie-Lise; Pagliarini, Samuel Nascimento2023 24th International Symposium on Quality Electronic Design (ISQED) : San Francisco, 5-7 April 20232023 / 8 p. : ill https://doi.org/10.1109/ISQED57927.2023.10129403 https://www.scopus.com/record/display.uri?eid=2-s2.0-85161555775&origin=resultslist&sort=plf-f&src=s&sid=d75ef4f2e771071f4016a3777c77ec72&sot=b&sdt=b&s https://www.webofscience.com/wos/woscc/full-record/WOS:001013619400077
• Reusing verification assertions as security checkers for Hardware Trojan detectionEslami, Mohammad; Ghasempouri, Tara; Pagliarini, Samuel Nascimento2022 23rd International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA : 06-07 April 20222022 / p. 1-6 : ill https://doi.org/10.1109/ISQED54688.2022.9806292
• SALSy : security-aware layout synthesisEslami, Mohammad; Perez, Tiago Diadami; Pagliarini, Samuel NascimentoarXiv.org2024 / 13 p. : ill https://doi.org/10.48550/arXiv.2308.06201
• SCARF : securing chips with a robust framework against fabrication-time hardware trojansEslami, Mohammad; Ghasempouri, Tara; Pagliarini, Samuel NascimentoIEEE Transactions on Computers2024 / p. 2761-2775 https://doi.org/10.1109/TC.2024.3449082 https://www.scopus.com/sourceid/25033 https://www.scopus.com/record/display.uri?eid=2-s2.0-85201752061&origin=resultslist&sort=plf-f&src=s&sot=b&sdt=b&s=TITLE-ABS-KEY%28%22SCARF%3A+Securing+Chips+With+a+Robust+Framework+Against+Fabrication-Time+Hardware+Trojans%22%29&sessionSearchId=7f45e0ec132af76c064c755f1de85733&relpos=0 https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20T%20COMPUT&year=2023 https://www.webofscience.com/wos/woscc/full-record/WOS:001351576000009
• SCARF : securing chips with a robust framework against fabrication-time hardware Trojans : preprintEslami, Mohammad; Ghasempouri, Tara; Pagliarini, Samuel NascimentoarXiv.org2024 / 14 p. : ill https://doi.org/10.48550/arXiv.2402.12162
• A security-aware and LUT-based CAD flow for the physical synthesis of hASICsAbideen, Zain Ul; Perez, Tiago Diadami; Martins, Mayler; Pagliarini, Samuel NascimentoIEEE transactions on computer-aided design of integrated circuits and systems2023 / p. 3157-3170 : ill https://doi.org/10.1109/TCAD.2023.3244879 https://www.scopus.com/sourceid/27724 https://www.scopus.com/record/display.uri?eid=2-s2.0-85149361558&origin=inward&txGid=dcdfac19b8c2e28e5d718affcdda7cc2 https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20T%20COMPUT%20AID%20D&year=2023 https://www.webofscience.com/wos/woscc/full-record/WOS:001071466500003
• Security-aware physical synthesis of integrated circuits = Integraallülituste turvateadlik füüsiline sünteesPerez, Tiago Diadami2023 https://doi.org/10.23658/taltech.4/2023 https://digikogu.taltech.ee/et/Item/440f41fd-0950-4b5c-8e47-4f75a754cdae https://www.ester.ee/record=b5536743*est
• Side-channel attacks on triple modular redundancy schemesAlmeida, Felipe; Aksoy, Levent; Raik, Jaan; Pagliarini, Samuel Nascimento2021 IEEE 30th Asian Test Symposium ATS 2021 : proceedings2021 / p. 79-84 : ill https://doi.org/10.1109/ATS52891.2021.00026 https://www.scopus.com/sourceid/14494 https://www.scopus.com/record/display.uri?eid=2-s2.0-85124706879&origin=inward&txGid=d523894835aa1e27e51a5c4020036746 https://www.webofscience.com/wos/woscc/full-record/WOS:000781836500014
• A side-channel hardware trojan in 65nm CMOS with 2μW precision and multi-bit leakage capabilityPerez, Tiago Diadami; Pagliarini, Samuel Nascimento2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) : 17-20 January 2022 : Taipei, Taiwan2022 / p. 9-10 : ill https://doi.org/10.1109/ASP-DAC52403.2022.9712490
• Side-channel Trojan insertion - a practical foundry-side attack via ECOPerez, Tiago Diadami; Imran, Malik; Vaz, Pablo; Pagliarini, Samuel Nascimento2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, May 22-28, 2021 : proceedings2021 / 5 p. : ill https://doi.org/10.1109/ISCAS51556.2021.9401481 https://www.scopus.com/sourceid/56190 https://www.scopus.com/record/display.uri?eid=2-s2.0-85109036293&origin=inward&txGid=ab42f2e6641a52d32027b1dc4f2126b6 https://www.webofscience.com/wos/woscc/full-record/WOS:000706507900007
• Split-chip design to prevent IP reverse engineeringPagliarini, Samuel Nascimento; Sweeney, Joseph; Mai, Ken; Blanton, Shawn; Mitra, Subhasish; Pileggi, LarryIEEE Design and Test2020 / p. 109-118 https://doi.org/10.1109/MDAT.2020.3033255 https://www.scopus.com/sourceid/21100286806 https://www.scopus.com/record/display.uri?eid=2-s2.0-85095985466&origin=inward&txGid=5cd9b065fa2590c9dd1c7c529d74978c https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20DES%20TEST&year=2022 https://www.webofscience.com/wos/woscc/full-record/WOS:000678331400021
• A survey on split manufacturing : attacks, defenses, and challengesPerez, Tiago Diadami; Pagliarini, Samuel NascimentoIEEE Access2020 / p. 184013-184035 https://doi.org/10.1109/ACCESS.2020.3029339 https://www.scopus.com/sourceid/21100374601 https://www.scopus.com/record/display.uri?eid=2-s2.0-85101841306&origin=inward&txGid=1abec245e5e8a6b34906241854d7052d https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20ACCESS&year=2022 https://www.webofscience.com/wos/woscc/full-record/WOS:000579348000001
• A systematic study of lattice-based NIST PQC algorithms : from reference implementations to hardware acceleratorsImran, Malik; Abideen, Zain Ul; Pagliarini, Samuel NascimentoarXiv.org2020 / 36 p. : ill
• Toimiva digiühiskonna tagavad usaldusväärne tarkvara, turvaline riistvara ning energiasäästlikud ja nutikad asjadHärmat, KarinMente et Manu2022 / lk. 32-33 https://www.ester.ee/record=b1242496*est
• A tutorial on design obfuscation : from transistors to systemsPagliarini, Samuel Nascimento2021 IEEE 22nd Latin American Test Symposium (LATS), Punta del Este, Uruguay, 27-29 October 20212021 / 3 p. : ill https://doi.org/10.1109/LATS53581.2021.9651741
• Uued inimesed TalTechisDashtimanesh, Abbas; Gerstlberger, Wolfgang Dieter; Hoffmann, Thomas; Männik, Aarne; Niidu, Allan; Pagliarini, Samuel Nascimento; Sobocinski, Pawel Maria; Treffner, IvarMente et Manu2019 / lk. 26-32 : fot https://www.ester.ee/record=b1242496*est
• A versatile and flexible multiplier generator for Large integer polynomialsImran, Malik; Abideen, Zain Ul; Pagliarini, Samuel NascimentoJournal of hardware and systems security2023 / p. 55–71 https://doi.org/10.1007/s41635-023-00134-2
• Võitlus kiipides varitsevate troojalastega tõstab Eesti teadlased kilbileHärmat, Karinerr.ee2023 https://novaator.err.ee/1609026488/voitlus-kiipides-varitsevate-troojalastega-tostab-eesti-teadlased-kilbile