Exploiting high-level descriptions for circuits fault tolerance assessments
autor
vastutusandmed
A.Benso, P.Prinetto, M.Rebaudengo, M.Sonza Reorda, J.Raik, R.Ubar
allikas
1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, October 20-22, 1997
ilmumiskoht
[S.l.]
kirjastus/väljaandja
ilmumisaasta
leheküljed
p. 212-216
keel
inglise
Benso, A., Prinetto, P., Rebaudengo, M., Sonza Reorda, M., Raik, J., Ubar, R. Exploiting high-level descriptions for circuits fault tolerance assessments // 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, October 20-22, 1997. [S.l.] : IEEE, 1997. p. 212-216.