prindi

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

autor
Oyeniran, Adeboye Stephen
Ubar, Raimund-Johannes
Jenihhin, Maksim
Raik, Jaan
vastutusandmed
Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
allikas
2019 IEEE European Test Symposium (ETS) : ETS 2019, May 27-31, 2019, Baden-Baden, Germany : Proceedings
ilmumiskoht
Danvers
kirjastus/väljaandja
IEEE
ilmumisaasta
2019
leheküljed
6 p. : ill
konverentsi toimumispaik
Baden-Baden, Germany
leitav
https://doi.org/10.1109/ETS.2019.8791526
võtmesõna
RISC processors
high-level fault model
high-level test data generation
deterministic and pseudo-exhaustive tests
control and data path tests
ISBN
978-1-7281-1173-5
märkused
Bibliogr.: 31 ref
TTÜ struktuuriüksus
arvutisüsteemide instituut
keel
inglise
Oyeniran, A.S., Ubar, R., Jenihhin, M., Gürsoy, C., Raik, J. High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors // 2019 IEEE European Test Symposium (ETS) : ETS 2019, May 27-31, 2019, Baden-Baden, Germany : Proceedings. Danvers : IEEE, 2019. 6 p. : ill. https://doi.org/10.1109/ETS.2019.8791526