Automatic SoC level test path synthesis based on partial functional models

vastutusandmed
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
allikas
2011 Asian Test Symposium (ATS) : New Delhi, India
ilmumiskoht
[S.l.]
ilmumisaasta
leheküljed
p. 532-538
konverentsi nimetus, aeg
2011 Asian Test Symposium (ATS)
konverentsi toimumispaik
New Delhi, India
võtmesõna
processor-centric board test
test path synthesis
PCBA component modeling
ISSN
1081-7735
keel
inglise
Tšertov, A., Ubar, R., Jutman, A., Devadze, S. Automatic SoC level test path synthesis based on partial functional models // 2011 Asian Test Symposium (ATS) : New Delhi, India. [S.l.], 2011. p. 532-538. https://ieeexplore.ieee.org/document/6114730