• Processor vulnerability detection with the aid of assertions : RISC-V case studyHeidari Iman, Mohammad Reza; Ahmadi-Pour, Sallar; Drechsler, Rolf; Ghasempouri, Taratechrxiv.org2024 / p. 1-8 : ill https://doi.org/10.36227/techrxiv.172101134.45466090/v1
• Processor vulnerability detection with the aid of assertions : RISC-V case studyHeidari Iman, Mohammad Reza; Ahmadi-Pour, Sallar; Drechsler, Rolf; Ghasempouri, Tara2024 IEEE Nordic Circuits and Systems Conference, NORCAS 2024 - Proceedings2024 / 7 p. https:/doi.org/10.1109/NorCAS64408.2024.10752460 https://www.scopus.com/pages/publications/85211947713?origin=resultslist https://www.webofscience.com/wos/woscc/full-record/WOS:001444043400023
• Reliability improvements for multiprocessor systems by health-aware task schedulingSchmidt, Robert; Massoud, Rehab; Raik, Jaan; Garcia-Ortiz, Alberto; Drechsler, Rolf2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS 2018) : 2 - 4 July 2018, Spain2018 / p. 247-250 : ill http://dx.doi.org/10.1109/IOLTS.2018.8474101
• Special session paper: Application of functional verification techniques in hardware trustHeidari Iman, Mohammad Reza; Drechsler, Rolf; Jha, Chandan Kumar; Azarpeyvand, Ali; Ghasempouri, Tara; Imtiaz, Sharjeel; Raik, Jaan; Germiniani, Samuele; Nicoletti, Daniele; Pravadelli, Graziano; Di Natale, Giorgio2025 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)2025 / 8 p. : ill https://ieeexplore.ieee.org/document/11257462 https://doi.org/10.1109/DFT66274.2025.11257462 https://www.scopus.com/sourceid/21101123252 https://www.scopus.com/pages/publications/105029688511?origin=resultslist