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- Arvuti nööpaugusAgur, UstusHorisont1976 / lk. 12-15 : ill https://www.ester.ee/record=b1072243*est http://www.digar.ee/id/nlib-digar:291330
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- Cal-Techist PocketronicuniToomsalu, ArvoA & A2005 / 4, lk. 9-12 https://artiklid.elnet.ee/record=b1018130*est
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- Circuit simulation program oriented physical modeling of integrated circuit elementsRang, Toomas; Tarnay, K.; Szekely, V.Periodica polytechnica. Electrical engineering = Электротехника1980 / p. 37-45 https://www.ester.ee/record=b1198855*est
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- Esimene üldkasutatav mikrokontrollerkiip TMS 1000Toomsalu, ArvoA & A2008 / 2, lk. 9-16 : ill
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- Fault diagnosis in VLSI devicesUbar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering1995 / 1, p. 51-67
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- I²L új irányrat a bipoláris technikában IRang, ToomasMérés és automatika: megjelenik a Méréstechnikai és Automatizálási Tudományos Egyesület Szerkesztésében1979 / p. 191-195
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- IEEE Norchip 2003. a. konverentsEllervee, PeeterA & A2004 / 1, lk. 48-49 https://artiklid.elnet.ee/record=b1015000*est
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- Improving the efficiency of timing simulation in digital circuits by using structurally synthesized BDDsUbar, Raimund-Johannes; Jutman, Artur; Peng, Z.IEEE Norchip Conference2000 / p. 254-261
- Informal Digest of Papers : 10 IEEE European Test Symposium : Tallinn, Estonia, May 22-25, 20052005 https://www.ester.ee/record=b2055139*est
- Integraallülituste hindToomsalu, ArvoA & A2007 / 3, lk. 20-32 : ill
- Integraallülituste pöördprojekteerimineToomsalu, ArvoA & A1998 / 2, lk. 8-13
- Integraalskeemide projekteerimine : metoodiline juhend1988 https://www.ester.ee/record=b1239938*est
- Integrált áramköri elemek fizikai modellezése aramkölanalizös program segítségévelRang, Toomas; Tarnay, K.; Szekely, V.Híradástechnika = Journal on communications, computers, convergence, contents, companies1980 / p. 322-326
- Intel 1103 - esimene DRAM-kiipToomsalu, ArvoA & A2006 / 5, lk. 27-32 https://artiklid.elnet.ee/record=b1019636*est
- Interaction between point defects, extended defects and impurities in the Si-SiO2 system during the process of its formationKropman, Daniel; Kärner, T.; Abru, Uno; Ugaste, Ülo; Mellikov, EnnThin solid films2004 / 1/2, p. 53-57 : ill https://www.sciencedirect.com/science/article/abs/pii/S0921510704003459
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- Kiibiargonaudid, nende kuldvillak ja sümplegaadidTammemäe, Kalle; Ellervee, PeeterInformaatika perspektiivsed suunad : Eesti Teaduste Akadeemia seminari materjalid : 29.11.20002000 / lk. 17-20 : ill
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- Быстродействующие интегральные компараторыGurjanov, Boris; Tamm, UljasIX Всесоюзная научно-техническая конференция по микроэлектронике, г. Казань, 14-17 окт. 1980 г. : тезисы докладов1980 / с. 88
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- Измеритель коэффициента шума интегральных усилителейTammet, Heinar; Torim, A.A.Тезисы докладов республиканской научно-технической конференции, посвященной 80-летию со дня изобретения радио А. С. Поповым1975 / с. 93 https://www.ester.ee/record=b1322122*est
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