- Fast test pattern generation for sequential circuits using decision diagram representationsRaik, Jaan; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications (JETTA)2000 / 3, p. 213-226 : ill https://link.springer.com/article/10.1023/A:1008335130158
- Identification and rejuvenation of NBTI-critical logic paths in nanoscale circuitsJenihhin, Maksim; Squillero, Giovanni; Tihhomirov, Valentin; Kostin, Sergei; Raik, Jaan; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications (JETTA)2016 / p. 273-289 : ill https://doi.org/10.1007/s10836-016-5589-x https://www.scopus.com/sourceid/18040 https://www.scopus.com/record/display.uri?eid=2-s2.0-84966714453&origin=inward&txGid=3b4ba7ac260a393cbe6bed59b4d314b9 https://jcr.clarivate.com/jcr-jp/journal-profile?journal=J%20ELECTRON%20TEST&year=2016 https://www.webofscience.com/wos/woscc/full-record/WOS:000377449900004
- Identifying untestable faults in sequential circuits using test path constraintsViilukas, Taavi; Karputkin, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Fujiwara, HideoJournal of electronic testing : theory and applications (JETTA)2012 / p. 511-521 : ill https://link.springer.com/article/10.1007/s10836-012-5312-5
- Optimization of boundary scan tests using FPGA-based efficient scan architecturesAleksejev, Igor; Devadze, Sergei; Jutman, Artur; Shibin, KonstantinJournal of electronic testing : theory and applications (JETTA)2016 / p. 245-255 : ill https://doi.org/10.1007/s10836-016-5588-y https://www.scopus.com/sourceid/18040 https://www.scopus.com/record/display.uri?eid=2-s2.0-84964452131&origin=inward&txGid=035b6825dd1a37b925ec9c823fcecd7d https://jcr.clarivate.com/jcr-jp/journal-profile?journal=J%20ELECTRON%20TEST&year=2016 https://www.webofscience.com/wos/woscc/full-record/WOS:000377449900002