• Fast RTL fault simulation using decision diagrams and bitwise set operationsReinsalu, Uljana; Raik, Jaan; Ubar, Raimund-Johannes; Ellervee, Peeter2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : 3-5 October 2011, Vancouver, Canada2011 / p. 164-170 https://ieeexplore.ieee.org/document/6104440
• Identifying untestable faults in sequential circuits using test path constraintsViilukas, Taavi; Karputkin, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Fujiwara, HideoJournal of electronic testing : theory and applications (JETTA)2012 / p. 511-521 : ill https://link.springer.com/article/10.1007/s10836-012-5312-5
• On the reuse of TLM mutation analysis at RTLGuarnieri, Valerio; Hantson, Hanno; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications2012 / p. 435-448 : ill https://link.springer.com/article/10.1007/s10836-012-5303-6
• SynAssert: automated synthesis of CSCA leakage patterns into cost-effective security assertionsAzarpeyvand, Ali Azarpeyvand; Eslami, Mohammad; Jervan, Gert; Raik, Jaan; Ghasempouri, TaraProceedings of 2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)2025 / 6 p. : ill https://doi.org/10.1109/ISVLSI65124.2025.11130310 https://www.scopus.com/sourceid/21100286357 https://www.scopus.com/pages/publications/105016199367?origin=resultslist https://www.webofscience.com/wos/woscc/full-record/WOS:001575951700061