An Accelerator-based architecture utilizing an efficient memory link for modern computational requirements

autor
Yousefzadeh, Saba
Basharkhah, Katayoon
vastutusandmed
Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi
allikas
2019 IEEE East-West Design & Test Symposium (EWDTS)
ilmumiskoht
[S.l.]
kirjastus/väljaandja
ilmumisaasta
leheküljed
6 p. : ill
konverentsi nimetus, aeg
2019 IEEE East-West Design & Test Symposium (EWDTS), 13-16 Sept. 2019
konverentsi toimumispaik
Batumi, Georgia
võtmesõna
accelerator-based architecture
on-chip communication architectures
ISSN
2472-761X
2373-826X
ISBN
978-1-7281-1003-5
978-1-7281-1004-2
märkused
Bibliogr.: 11 ref
TTÜ struktuuriüksus
keel
inglise
Yousefzadeh, S., Basharkhah, K., Raik, J., Jenihhin, M. et al. An Accelerator-based architecture utilizing an efficient memory link for modern computational requirements // 2019 IEEE East-West Design & Test Symposium (EWDTS). [S.l.] : IEEE, 2019. 6 p. : ill. https://doi.org/10.1109/EWDTS.2019.8884481