A generic synthesizable NoC switch with a scalable testbenchGovind, Vineeth; Raik, Jaan; Ubar, Raimund-JohannesBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 91-94 : ill

A new testability calculation method to guide RTL test generationRaik, Jaan; Nõmmeots, Tanel; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications2005 / 1, p. 71-82 : ill https://link.springer.com/article/10.1007/s10836-005-5288-5

A PC-based CAD system for training digital testUbar, Raimund-Johannes; Buldas, Ahto; Paomets, Priidu; Raik, Jaan; Tulit, ViljarThe Fifth EUROCHIP Workshop on VLSI Design Training, 17-18-19 October 1994, Dresden, Germany1994 / p. 152-157: ill

A scalable model based RTL framework zamiaCAD for static analysisTšepurov, Anton; Jenihhin, Maksim; Raik, Jaan; Tihhomirov, Valentin2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) : October 7-10, 2012 Santa Cruz, USA Dream Inn, Santa Cruz, USA : [proceedings]2012 / p. 171-176 : ill

A scalable static test set compaction method for sequential circuitsAleksejev, Igor; Raik, Jaan; Jutman, Artur; Ubar, Raimund-JohannesProceedings of the 9th IEEE Latin-American Test Workshop : LATW2008 : February 17-20, 2008, Puebla, Mexico2008 / p. 87-92 : ill

A scalable technique to identify true critical paths in sequential circuitsUbar, Raimund-Johannes; Kostin, Sergei; Jenihhin, Maksim; Raik, JaanProceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany2017 / p. 152-157 : ill https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553

A synthesis-agnostic behavioral fault model for high gate-level fault coverageKarputkin, Anton; Raik, JaanProceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) : 14-18 March 2016, ICC, Dresden, Germany2016 / p. 1124-1127 : ill https://ieeexplore.ieee.org/document/7459477/figures#figures

A tool for random test generation targeting high diagnostic resolutionOsimiry, Emmanuel Ovie; Kostin, Sergei; Raik, Jaan; Ubar, Raimund-JohannesBEC 2016 : 2016 15th Biennial Baltic Electronics Conference : proceedings of the 15th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 3-5, 2016, Tallinn, Estonia2016 / p. 79-82 : ill http://www.ester.ee/record=b2150914*est

About robustness of test patterns regarding multiple faultsUbar, Raimund-Johannes; Kostin, Sergei; Raik, JaanLATW 2012 : 13th IEEE Latin-American Test Workshop proceedings : April 10th-13th, 2012, Quito, Ecuador2012 / p. 86-91 : ill

Abstraction of clock interface for conversion of RTL VHDL to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, Jaan2014 IEEE International Advance Computing Conference (IACC) : February 21-22, 2014, Gurgaon, India2014 / p. 50-55 : ill

Accelerating transient fault injection campaigns by using Dynamic HDL SlicingBagbaba, Ahmet Cagri; Jenihhin, Maksim; Raik, Jaan; Sauer, Christian2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore2019 / 7 p. : ill https://doi.org/10.1109/NORCHIP.2019.8906932

Accurate NBTI-induced gate delay modeling based on intensive SPICE simulationsKostin, Sergei; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, MaksimMEDIAN Finale : Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : November 10-11, 2015, Tallinn, Estonia2015 / p. 21-26 : ill

Adaptive Kalman filter based data aggregation in fault-resilient Underwater Sensor NetworksVihman, Lauri; Raik, Jaan2023 24th International Conference on Digital Signal Processing (DSP)2023 / p. 1-5 https://doi.org/10.1109/DSP58604.2023.10167982

Adjustable self-healing methodology for accelerated functions in heterogeneous systemsRiazati, Mohammad; Ghasempouri, Tara; Daneshtalab, Masoud; Raik, Jaan; Sjodin, Mikael; Lisper, Bjorn2020 23rd Euromicro Conference on Digital System Design (DSD), 26-28 August 2020, Kranj, Slovenia2020 / p. 638-645 https://doi.org/10.1109/DSD51259.2020.00104

Advanced technical education in the age of cyber physical systemsVierhaus, Heinrich Theodor; Schölzel, Mario; Raik, Jaan; Ubar, Raimund-Johannes10th European Workshop on Microelectronics Education : EWME 2014 : May 14-16, 2014, Tallinn, Estonia2014 / p. 193-198 : ill

Algorithms for hierarchical fault simulation in digital systemsUbar, Raimund-Johannes; Raik, Jaan; Klüver, B.Proceedings of the 10th International Conference : Mixed Design of Integrated Circuits and Systems : MIXDES 2003 : Lodz, Poland, 26-28 June 20032003 / p. 530-535 : ill

Algorithms for online CO2 baseline correction in intermittently occupied roomsVihman, Lauri; Parts, Tuule Mall; Aljas, Hans Kristjan; Thalfeldt, Martin; Raik, JaanHealthy Buildings 2023 Europe: Beyond Disciplinary Boundaries: proceedings ; 12023 / p. 302-309 : ill https://www.proceedings.com/content/070/070278webtoc.pdf

An Accelerator-based architecture utilizing an efficient memory link for modern computational requirementsYousefzadeh, Saba; Basharkhah, Katayoon; Raik, Jaan; Jenihhin, Maksim2019 IEEE East-West Design & Test Symposium (EWDTS)2019 / 6 p. : ill https://doi.org/10.1109/EWDTS.2019.8884481

An approach for PSL assertion coverage analysis with high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Shchenova, TatjanaProceedings of IEEE East-West Design & Test Symposium (EWDTS'10) : St. Petersburg, Russia, September 17-20, 20102010 / p. 13-16 : ill https://ieeexplore.ieee.org/document/5742048

An approach for verification assertions reuse 2 in RTL test pattern generationJenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi; Fujiwara, HideoJournal of Shanghai Normal University : Natural Sciences2010 / p. 441-447 : ill https://www.researchgate.net/publication/240613999_An_Approach_for_Verification_Assertions_Reuse_in_RTL_Test_Pattern_Generation

An approach for verification assertions reuse in RTL test pattern generationJenihhin, Maksim; Raik, Jaan; Fujiwara, Hideo; Ubar, Raimund-Johannes; Viilukas, TaaviDigest of papers : IEEE 11th Workshop on RTL and High Level Testing : WRTLT'10 : December 5-6, 2010, Shanghai, China2010 / p. 107-110 : ill

An automatic approach to evaluate assertions' quality based on data-mining metricsGhasempouri, Tara; Niazmand, Behrad; Raik, JaanProceedings 2nd IEEE International Test Conference in Asia : ITC-Asia 2018, 15-17 August 2018, Harbin, China2018 / p. 61-66 : ill https://doi.org/10.1109/ITC-Asia.2018.00021

An educational environment for digital testing : hardware, tools, and web-based runtime platformJutman, Artur; Raik, Jaan; Ubar, Raimund-Johannes; Vislogubov, VladislavProceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 412-419 : ill

An external diagnosis method for network-on-a-chipRaik, Jaan; Govind, Vineeth; Ubar, Raimund-JohannesIEEE/ACM Design Automation and Test in Europe, Workshop on Diagnostic Services in Networks-on-Chips - Test, Debug and On-line Monitoring : April 16-20, 2007, Nice, France2007 / [2] p. : ill

An external test approach for network-on-a-chip switchesRaik, Jaan; Govind, Vineeth; Ubar, Raimund-JohannesATS '06 : Proceedings of the 15th Asian Test Symposium : November 20-23, 2006, Fukuoka, Japan2006 / p. 437-442 : ill http://dx.doi.org/10.1109/ATS.2006.23

An external test approach for network-on-a-chip switchesRaik, Jaan; Govind, Vineeth; Ubar, Raimund-Johannes2002-2011 : 20th Anniversary compendium of papers from Asian Test Symposium2011 / p. 185-190 : ill

An XML-based test development and deployment framework for mixed-signal and digital devicesMellik, Andres; Raik, Jaan2008 IEEE AUTOTESTCON. Vols. 1 and 22008 / p. 193-196

Application of high-level decision diagrams for simulation-based verification tasksJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesEstonian journal of engineering2010 / 1, p. 56-77 : ill

Application of sequential test set compaction to LFSR reseedingAleksejev, Igor; Jutman, Artur; Raik, Jaan; Ubar, Raimund-Johannes26th Norchip Conference : Tallinn, Estonia, 17-18 November 2008 : formal proceedings2008 / p. 102-107 : ill http://dx.doi.org/10.1109/NORCHP.2008.4738292

Application specific true critical paths identification in sequential circuitsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Oyeniran, Adeboye Stephen2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019) : 1-3 July 2019, Greece2019 / p. 299-304 : ill https://doi.org/10.1109/IOLTS.2019.8854442

Applications of the open source HW design framework zamiaCADTšepurov, Anton; Tihhomirov, Valentin; Saif Abrar, Syed; Jenihhin, Maksim; Raik, JaanDATE 2012 University Booth : Design Automation and Test in Europe : Dresden, Germany, March 12-16, 20122012 / 1 p

APPRAISER : DNN fault resilience analysis employing approximation errorsTaheri, Mahdi; Ahmadilivani, Mohammad Hasan; Jenihhin, Maksim; Raik, Jaan; Daneshtalab, Masoud26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, May 3-5, 2023, Tallinn2023 / p. [?] https://ddecs2023.taltech.ee/

Approaches to extra-functional verification of security and reliability aspects in hardware designs = Riistvaraprojektide turva- ja töökindlusaspektide ekstrafunktsionaalse verifitseerimise lähenemisviisidLai, Xinhui2022 https://doi.org/10.23658/taltech.29/2022 https://digikogu.taltech.ee/et/Item/cff1aeb9-b0b2-49ce-b81a-bfb9dc25fd56 https://www.ester.ee/record=b5502807*est

APRICOT : a framework for teaching digital systems verificationRaik, Jaan; Jenihhin, Maksim; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-Johannes19th EAEEIE Annual Conference : June 29-July 2, 2008, Tallinn, Estonia : formal proceedings2008 / p. 172-177 : ill http://dx.doi.org/10.1109/EAEEIE.2008.4610181

Assembling low-level tests to high-level symbolic test framesJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings [of the] 15th NORCHIP Conference, Tallinn, 10-11 November 19971997 / p. 275-280: ill

Assertion checking with PSL and high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesDigest of papers IEEE 8th Workshop on RTL and High Level Testing : WRTLT'07 : October 12-13, 2007, Beijing, China2007 / p. 105-110 : ill https://pld.ttu.ee/~maksim/phd_papers/%5B12%5D%20wrtlt%2707.pdf

Assessment of diagnostic test for automated bug localizationTihhomirov, Valentin; Tšepurov, Anton; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-JohannesLATW2013 : 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013 : [proceedings]2013 / [6] p. : ill

Assessment of electroencephalographic measures applied in the detection of depression = Depressiooni avastamiseks kasutatavate elektroentsefalograafilise signaali mõõdikute analüüsPäeske, Laura2021 https://www.ester.ee/record=b5411747*est https://digikogu.taltech.ee/et/Item/44751b09-b47f-4757-847f-dd0f1d39b91b https://doi.org/10.23658/taltech.17/2021

At-speed self-testing of high-performance pipe-lined processing architectures [Electronic resource]Gorev, Maksim; Ubar, Raimund-Johannes; Ellervee, Peeter; Devadze, Sergei; Raik, Jaan; Min, Mart31st Norchip Conference : Vilnius, Lithuania, 11-12 November 2013 : conference program and papers2013 / p. 1-6 : ill [USB]

Automated area and coverage optimization of minimal latency checkersAzad, Siavoosh Payandeh; Niazmand, Behrad; Apneet Kaur; Raik, Jaan; Jervan, Gert; Hollstein, Thomas2017 22nd IEEE European Test Symposium (ETS 2017), Limassol, Cyprus, 22 – 26 May 2017 : proceedings2017 / p. 7-8 : ill https://doi.org/10.1109/ETS.2017.7968211

Automated correction of design errors by edge redirection on high-level decision diagramsKarputkin, Anton; Ubar, Raimund-Johannes; Tombak, Mati; Raik, Jaan13th International Symposium on Quality Electronic Design (ISQED), 20122012 / p. 686-693 : ill https://ieeexplore.ieee.org/document/6113980

Automated design error debug using high-level decision diagrams and mutation operatorsRaik, Jaan; Repinski, Urmas; Tšepurov, Anton; Hantson, Hanno; Ubar, Raimund-Johannes; Jenihhin, MaksimMicroprocessors and microsystems2013 / p. 505-513 : ill

Automated design error localization in RTL designsJenihhin, Maksim; Tšepurov, Anton; Tihhomirov, Valentin; Raik, Jaan; Hantson, Hanno; Ubar, Raimund-Johannes; Bartsch, Günter; Meza Escobar, Jorge Hernan; Wuttke, Heinz-DietrichIEEE design & test of computers2014 / p. 83-92 : ill http://dx.doi.org/10.1109/MDAT.2013.2271420

An automated method for mining high-quality assertion setsHeidari Iman, Mohammadreza; Raik, Jaan; Jenihhin, Maksim; Jervan, Gert; Ghasempouri, TaraMicroprocessors and microsystems2023 / art. 104773 https://doi.org/10.1016/j.micpro.2023.104773

Automated minimization of concurrent online checkers for network-on-chipsSaltarelli, Pietro; Niazmand, Behrad; Hariharan, Ranganathan; Raik, Jaan; Jervan, Gert; Hollstein, Thomas10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip (ReCoSoC 2015) : Bremen, 29 June - 1 July 20152015 / [8] p. : ill http://dx.doi.org/10.1109/ReCoSoC.2015.7238079

Automated test bench generation for high-level synthesis flow ABELITEViilukas, Taavi; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Baranov, SamaryProceedings of IEEE East-West Design & Test Symposium (EWDTS'2011) : Sevastopol, Ukraine, September 9-12, 20112011 / p. 13-16 : ill https://ieeexplore.ieee.org/document/6116601

Automated test pattern generator with constraint solverViilukas, Taavi; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / lk. 33-36

Automatic generation of EFSMs and HLDDs for functional ATPGTšepurov, Anton; Guglielmo, Giuseppe di; Raik, Jaan; Ubar, Raimund-Johannes; Viilukas, TaaviBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 143-146 : ill

Automatic test generation system for VLSIJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the First Electronic Circuits and Systems Conference : Bratislava, Slovakia, September 4-5, 19971997 / p. 255-258

AWAIT : an ultra-lightweight soft-error mitigation mechanism for network-on-chip linksJanson, Karl; Pihlak, Rene; Azad, Siavoosh Payandeh; Niazmand, Behrad; Jervan, Gert; Raik, Jaan2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille, France, July 9th-11th, 20182018 / p. 1-6 : ill https://doi.org/10.1109/ReCoSoC.2018.8449374

Back-tracing and event-driven techniques in high-level simulation with decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Morawiec, AdamISCAS 2000 Geneva : The 2000 IEEE International Symposium on Circuits and Systems : Emerging Technologies for the 21st Century : May 28-31, 2000 : proceedings. Vol. 12000 / p. I-208 - I-211

BASTION : board and SoC test instrumentation for ageing and no failure foundJutman, Artur; Lotz, Christophe; Larsson, Erik; Sonza Reorda, Matteo; Jenihhin, Maksim; Raik, JaanProceedings of the 2017 Design, Automation & Test in Europe (DATE) : 27-31 March 2017, Swisstech, Lausanne, Switzerland2017 / p. 115-120 : ill https://doi.org/10.23919/DATE.2017.7926968

Block-level fault model-free debug and diagnosis in digital systemsUbar, Raimund-Johannes; Kostin, Sergei; Raik, JaanProceedings of the 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools : Patras, Greece, August 27-29, 20092009 / p. 229-232 https://ieeexplore.ieee.org/document/5350128

Built-in self diagnosis with multiple signature analyzers in digital systemsUbar, Raimund-Johannes; Kostin, Sergei; Raik, JaanProceedings of the 9th IEEE Latin-American Test Workshop : LATW2008 : February 17-20, 2008, Puebla, Mexico2008 / p. 29-34 : ill

CAD software for digital test and diagnosticsJervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesProceedings of International Conference on Design and Diagnostics of Electronic Circuits and Systems, Ostrava, Czech Republik, May 12-14, 19971997 / p. 35-40

A CAD system for teaching digital testUbar, Raimund-Johannes; Ivask, Eero; Paomets, Priidu; Raik, JaanBEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia). 11994 / p. 369-372: ill

Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanMicroprocessors and microsystems2020 / art. 103117, 12 p https://doi.org/10.1016/j.micpro.2020.103117 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Calculation of testability measures on structurally synthesized binary decision diagramsUbar, Raimund-Johannes; Heinlaid, J.; Raik, Jaan; Raun, L.BEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 179-182: ill

Calculation of the diagnosibility of digital circuits without using fault modelsUbar, Raimund-Johannes; Kostin, Sergei; Raik, JaanBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 159-162 : ill

Canonical representations of high-level decision diagramsKarputkin, Anton; Ubar, Raimund-Johannes; Raik, Jaan; Tombak, MatiEstonian journal of engineering2010 / 1, p. 39-55 : ill

CLD : an accurate, cost-effective and scalable run-time Cache Leakage DetectorShalabi, Ameer; Ghasempouri, Tara; Ellervee, Peeter; Raik, Jaan2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : Vienna, Austria, 07-09 April 20212021 / p. 127-132 : ill https://doi.org/10.1109/DDECS52668.2021.9417071

Code coverage analysis for concurrent programming languages using high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesProceedings of the 12th European Workshop on Dependable Computing : EWDC 2009 : Toulouse, France, May 14-15, 20092009 / [4] p. : ill https://hal.archives-ouvertes.fr/hal-00381559

Code coverage analysis using high-level decision diagrams [Electronic resource]Raik, Jaan; Reinsalu, Uljana; Ubar, Raimund-Johannes; Jenihhin, Maksim; Ellervee, Peeter2008 IEEE Design and Diagnostics of Electronic Circuits and Systems : Bratislava, Slovakia, April 16-18, 20082008 / p. 201-207 : ill. [CD-ROM]

Combined fault-model free cause-effect and effect-cause fault diagnosis in block-level digital networksUbar, Raimund-Johannes; Kostin, Sergei; Raik, JaanASQED'09 : 1st Asia Symposium on Quality Electronic Design : Kuala Lumpur, Malaisia, July 15-16, 20092009 / p. 385-390 https://ieeexplore.ieee.org/document/5206232

Combining dynamic slicing and mutation operators for ESL correctionRepinski, Urmas; Hantson, Hanno; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-JohannesProceedings : 2012 17th IEEE European Test Symposium (ETS) : May 28th-June 1st, 2012, Annecy, France2012 / [6] p. : ill

Combining learning, training and research in laboratory course for design and testUbar, Raimund-Johannes; Orasson, Elmet; Raik, Jaan; Wuttke, Heinz-DietrichThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 221-224 : ill

Comparative analysis of sequential circuit test generation approachesRaik, Jaan; Krivenko, Anna; Ubar, Raimund-JohannesBEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia2004 / p. 225-228 : ill

Comparative mixed-signal test method and toolsetMellik, Andres; Raik, JaanIEEE International Workshop on Open Source Test Technology Tools (IOST3)2007 / ? p

Comparison of genetic and random techniques for test pattern generationIvask, Eero; Raik, Jaan; Ubar, Raimund-JohannesBEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 163-166: ill

Comparison of model-based error localization algorithms for C designsRepinski, Urmas; Raik, JaanProceedings of IEEE East-West Design & Test Symposium (EWDTS’2012) : Kharkov, Ukraine, September 14–17, 20122012 / p. 42-45

Comprehensive abstraction of VHDL RTL cores to ESL SystemC = Register-siirde taseme VHDL kirjelduste kompleksne abstraheerimine süsteemitaseme SystemC mudeliteksAbrar, Syed Saif2016 http://www.ester.ee/record=b4564850*est

Comprehensive performance and robustness analysis of 2D turn models for network-on-chipsAzad, Siavoosh Payandeh; Niazmand, Behrad; Janson, Karl; Kogge, Thilo; Raik, Jaan; Jervan, Gert; Hollstein, Thomas2017 IEEE International Symposium on Circuits and Systems (ISCAS)2017 / p. 1476-1479 : ill https://doi.org/10.1109/ISCAS.2017.8050634

Constraint-based hierarchical untestability identification for synchronous sequential circuitsRaik, Jaan; Rannaste, Anna; Jenihhin, Maksim; Viilukas, Taavi; Ubar, Raimund-Johannes; Fujiwara, HideoSixteenth IEEE European Test Symposium : 23-27 May 2011, Trondheim2011 / p. 147-152

Constraint-based hierarchical untestability identification for syncronous sequential circuitsViilukas, Taavi; Raik, Jaan; Ubar, Raimund-Johannes; Rannaste, Anna; Jenihhin, Maksim; Fujiwara, HideoInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK viienda aastakonverentsi artiklite kogumik : 25.-26. novembril 2011, Nelijärve2011 / p. 139-142 : ill

Constraint-based test pattern generation at the register-transfer levelViilukas, Taavi; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Krivenko, AnnaProceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 14-16, 2010, Vienna, Austria2010 / p. 352-357 : ill http://dx.doi.org/10.1109/DDECS.2010.5491752

A constraint-driven gate-level test generatorRaik, Jaan; Ubar, Raimund-Johannes; Jervan, Gert; Krupnova, HelenaBEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 237-240: ill

Constraints solving based hierarchical test generation for synchronous sequential circuits = Kitsenduste lahendamisel baseeruv hierarhiline testigenereerimine sünkroonsetele järjestikskeemideleViilukas, Taavi2012 https://www.ester.ee/record=b2888278*est

Cost-effective concurrent hardware checkers for network on chip based system on chip = Kulutõhusad süsteemiga paralleelsed rikkemonitorid kiipvõrkudel põhinevatele kiipsüsteemideleHariharan, Ranganathan2019 https://digi.lib.ttu.ee/i/?12854

Critical path tracing based simulation of transition delay faultsKõusaar, Jaak; Ubar, Raimund-Johannes; Devadze, Sergei; Raik, JaanProceedings of the 8th Annual Conference of the Estonian National Doctoral School in Information and Communication Technologies : December 5-6, 2014, Rakvere2014 / p. 61-66 : ill

Critical path tracing based simulation of transition delay faultsKõusaar, Jaak; Ubar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan2014 17th Euromicro Conference on Digital System Design : DSD 2014 : 27-29 August 2014, Verona, Italy : proceedings2014 / p. 108-113 : ill

Cross-layer dependability management in network on chip based system on chip = Kiipvõrkudel põhinevate süsteemide kihtideülene usaldatavuse haldusAzad, Siavoosh Payandeh2018 https://digi.lib.ttu.ee/i/?9948

Cycle-based simulation algorithms for digital systems using high-level decision diagramsMorawiec, Adam; Ubar, Raimund-Johannes; Raik, JaanDesign, Automation and Test in Europe : Conference and Exhibition 2000 : Paris, France, March 27-30, 2000 : proceedings2000 / p. 743

Cycle-based simulation with decision diagramsUbar, Raimund-Johannes; Morawiec, Adam; Raik, JaanDesign, Automation and Test in Europe : DATE : Conference and Exhibition 1999 : Munich, Germany, March 9-12, 1999 : proceedings1999 / p. 454-458: ill

Data-driven cross-layer fault management architecture for sensor networksVihman, Lauri; Kruusmaa, Maarja; Raik, Jaan16th European Dependable Computing Conference : EDCC 2020 : Virtual Conference, Munich, Germany, 7-10 September 2020 : proceedings2020 / art. 20094188, p. 33-40 https://doi.org/10.1109/EDCC51268.2020.00015

Data-driven fault-resilient cross-layer sensor network architecture = Andmepõhine tõrkekindel kihtideülene sensorvõrgu arhitektuurVihman, Lauri2024 https://www.ester.ee/record=b5657135*est https://digikogu.taltech.ee/et/Item/00a93258-dc0f-4a4d-822f-099fff757224 https://doi.org/10.23658/taltech.7/2024

DECIDER : a decision diagram based hierarchical test generation systemJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 2nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Szczyrk, Poland, September 2-4, 19981998 / p. 269-273

DECIDER : a system for hierarchical test pattern generationRaik, Jaan; Ubar, Raimund-JohannesRadioelectronics and informatics2003 / p. 40-45 : ill

A decision diagram based hierarchical test pattern generatorJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesBEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 159-162: ill

Deductive fault simulation on structurally synthesized BDDsAarna, Margit; Ubar, Raimund-Johannes; Raik, JaanBEC 2004 : Baltic Electronics Conference : Post-Graduate Student Session : Tallinn University of Technology, October 3-6, 2004, Tallinn, Estonia2004 / p. 11 : ill

DeepAxe : a framework for exploration of approximation and reliability trade-offs in DNN acceleratorsTaheri, Mahdi; Riazati, Mohamad; Ahmadilivani, Mohammad Hasan; Jenihhin, Maksim; Daneshtalab, Masoud; Raik, Jaan; Sjödin, Mikael; Lisper, BjörnarXiv.org2023 / 8 p. : ill https://doi.org/10.48550/arXiv.2303.0822

Defect oriented fault coverage of 100stuck-at fault test setsBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 7th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2000 : Gdynia, Poland, 15-17 June 20002000 / p. 511-516 : ill

Defect-oriented BIST quality analysisKruus, Helena; Ubar, Raimund-Johannes; Raik, JaanBEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia2010 / p. 153-156 : ill

Defect-oriented fault simulation and test generation in digital circuitsKuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE ISQED 2001 : proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design : March 26-28, 2001, San Jose, California2001 / p. 365-371

Defect-oriented library builder and hierarchical test generationCibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS 2001 : Fourth International Workshop on IEEE Design and Diagnostics of Electronic Circuits and Systems : Györ, Hungary, April 18-20, 20012001 / p. 163-168 : ill

Defect-oriented mixed-level fault simulation in digital systemsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaFacta Universitatis [Niš]. Series electronics and energetics2002 / 1, April, p. 123-136 : ill

Defect-oriented modul-level fault diagnosis in digital circuitsKostin, Sergei; Ubar, Raimund-Johannes; Raik, JaanProceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 13-15, 2011, Gottbus, Germany2011 / p. 81-86

Defect-oriented test- and layout-generation for standard-cell ASIC designsSudbrock, Joachim; Raik, Jaan; Ubar, Raimund-Johannes; Kuzmicz, Wieslaw; Pleskacz, Witold A.Proceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 79-82 : ill

Defect-oriented test generation using probabilistic estimationCibakova, Tatiana; Fischerova, Maria; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 20002001 / p. 131-136 : ill

Dependability evaluation in fault-tolerant systems with high-level decision diagramsUbar, Raimund-Johannes; Jervan, Gert; Raik, Jaan; Jenihhin, Maksim; Ellervee, PeeterComputer Science Meets Automation : 10-13 September 2007 : proceedings. Volume II2007 / p. 147-152 : ill https://www.db-thueringen.de/receive/dbt_mods_00008864

Dependability improvements of NoC-based systems = Töökindluse parandamine kiipvõrkudel põhinevates süsteemidesNiazmand, Behrad2018 https://digi.lib.ttu.ee/i/?9879

Dependence of the EEG nonlinear coupling on the frequency bands and the segment lengthsOrgo, Laura; Bachmann, Maie; Kalev, Kaia; Järvelaid, Mari; Raik, Jaan; Hinrikus, HiieEMBEC & NBC 2017 : joint conference of the European Medical and Biological Engineering Conference (EMBEC) and the Nordic-Baltic Conference on Biomedical Engineering and Medical Physics (NBC), Tampere, Finland, June 20172018 / p. 799-802 https://doi.org/10.1007/978-981-10-5122-7_200

Design and test technology for dependable systems-on-chip2011 https://www.ester.ee/record=b4467408*est

Design error diagnosis using backtrace algorithm on decision diagramsRepinski, Urmas; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, Maksim; Tšepurov, AntonInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / p. 93-96

Design space exploration of SABER in 65nm ASICImran, Malik; Almeida, Felipe; Raik, Jaan; Basso, Andrea; Roy, Sujoy Sinha; Pagliarini, Samuel NascimentoASHES '21 : proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security2021 / p. 85-90 https://doi.org/10.1145/3474376.3487278

Design understanding : from logic to specificationFey, Goerschwin; Ghasempouri, Tara; Jacobs, Swen; Raik, JaanProceedings of the 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) : October 8-10, 2018, Verona, Italy2018 / p. 172–175 : ill https://doi.org/10.1109/VLSI-SoC.2018.8644732

Design-for-destability-based external test and diagnosis of mesh-like network- on-a-chipsRaik, Jaan; Govind, Vineeth; Ubar, Raimund-JohannesIET computers and digital techniques2009 / 5, p. 476-486 : ill http://dx.doi.org/10.1049/iet-cdt.2008.0096

Design-for-testability for application of external test patterns in a NoCGovind, Vineeth; Raik, Jaan2nd Workshop on Diagnostic Services in Network-on-Chips - Test, Debug, and On-Line Monitoring, in conjunction with Design Automation Conference (DAC)2008 / [4] p

Designing reliable cyber-physical systemsAleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; Devadze, Sergei; Jenihhin, Maksim; Jutman, Artur; Raik, Jaan; Shibin, KonstantinLanguages, design methods, and tools for electronic system design : selected contributions from FDL 20162018 / p. 15-38 : ill https://doi.org/10.1007/978-3-319-62920-9_2 Conference Proceedings at Scopus Article at Scopus

Designing reliable cyber-physical systems : overview associated to the special session at FDL'16Aleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; Devadze, Sergei; Jenihhin, Maksim; Jutman, Artur; Raik, Jaan; Shibin, KonstantinThe 2016 Forum on Specification & Design Languages : proceedings : Bremen, Germany, September 14-16, 20162016 / [8] p. : ill https://doi.org/10.1109/FDL.2016.7880382

Deterministic defect-oriented test generation for combinational circuitsRaik, Jaan; Ubar, Raimund-Johannes; Sudbrock, Joachim; Kuzmicz, Wieslaw; Pleskacz, Witold A.LATW 2005 : 6th IEEE Latin-American Test Workshop : March 30 - April 2, 2005, Salvador, Bahia, Brazil : [digest of papers]2005 / p. 325-330 : ill

DfT for application of external test patterns in a Network-on-a-ChipGovind, Vineeth; Raik, Jaan; Ubar, Raimund-JohannesInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / p. 25-28 : ill

DfT-based external test and diagnosis of mesh-like networks on chips = Testitavusel põhinev välise testi ja diagnoosi meetod kahemõõtmelistele kiipvõrkudeleGovind, Vineeth2009 https://digi.lib.ttu.ee/i/?454 https://www.ester.ee/record=b2539211*est

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysisHantson, Hanno; Repinski, Urmas; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-JohannesLATW 2012 : 13th IEEE Latin-American Test Workshop proceedings : April 10th-13th, 2012, Quito, Ecuador2012 / [6 p.] : ill

Diagnostic modeling of digital systems with multi-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, MaksimDesign and test technology for dependable systems-on-chip2011 / p. 92-118 : ill

Diagnostic modeling of microprocessors with high-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, Maksim; Brik, Marina; Istenberg, Martin; Wuttke, Heinz-DietrichBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 147-150 : ill

Diagnostic modelling of digital systems with binary and high-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Kruus, Helena; Lensen, Harri; Evartson, TeetProgress in industrial mathematics at ECMI 20062008 / p. 902-907 : ill

Diagnostic modelling of digital systems with multi-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Evartson, Teet; Kruus, Margus; Lensen, HarriProceedings of the 17th IASTED International Conference on Modelling and Simulation : May 24-26, 2006, Montreal, Quebec, Canada2006 / p. 207-212 : ill

Diagnostic software with WEB interface for teaching purposesVislogubov, Vladislav; Jutman, Artur; Kruus, Helena; Orasson, Elmet; Raik, Jaan; Ubar, Raimund-JohannesBEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia2004 / p. 255-258 : ill

Diagnostic test generation for statistical bug localization using evolutionary computationGaudesi, Marco; Jenihhin, Maksim; Raik, Jaan; Tihhomirov, Valentin; Ubar, Raimund-JohannesApplications of Evolutionary Computation : 17th European Conference, EvoApplications 2014, Granada, Spain, April 23-25, 2014 : revised selected papers2014 / p. 425-436 : ill

DIAGNOZER : a laboratory tool for teaching research in diagnosis of electronic systems [Electronic resource]Ubar, Raimund-Johannes; Kostin, Sergei; Jutman, Artur; Raik, Jaan; Wuttke, Heinz-Dietrich2009 IEEE International Conference on Microelectronic Systems Education MSE '09 : 25-27 July 2009, San Francisco, California : [proceedings]2009 / p. 12-15 : ill. [CD-ROM] http://dx.doi.org/10.1109/MSE.2009.5270842

Digitaalkiipide projekteerimine ja test : teadus, tehnoloogia või kunstRaik, JaanA & A2005 / lk. 5-9

Digital design flow with test activitiesDiener, Karl-Heinz; Elst, G.; Ivask, Eero; Jervan, Gert; Peng, Z.; Raik, Jaan; Ubar, Raimund-JohannesVILAB User Forum2000 / [11] p

Digital electronics design and test at Computer Engineering Department of Tallinn University of TechnologyUbar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Ellervee, PeeterThe house magazine : the parlamentary weekly2006 / 1198, p. 42 : ill

Digital logic simulation with compressed BDDsUbar, Raimund-Johannes; Mironov, Dmitri; Devadze, Sergei; Raik, JaanProceedings : 2011 IEEE International Conference on Computer Science and Automation Engineering : June 10-12, 2011, Shanghai, China2011 / p. 105-109 : ill

Distributed approach for genetic test generation in the field of digital electronicsIvask, Eero; Raik, Jaan; Ubar, Raimund-JohannesIntelligent Distributed Computing, Systems and Applications : proceedings of the 2nd International Symposium on Intelligent Distributed Computing : IDC 2008 : Catania, Italy, 20082008 / p. 127-136

DOT: new deterministic defect-oriented ATPG toolRaik, Jaan; Ubar, Raimund-Johannes; Sudbrock, Joachim; Kuzmicz, Wieslaw; Pleskacz, Witold A.European Test Symposium : ETS 2005 : 22-25 May 2005, Tallinn, Estonia : proceedings2005 / p. 96-101 : ill

EEG functional connectivity detects seasonal changesPäeske, Laura; Bachmann, Maie; Raik, Jaan; Hinrikus, HiieWorld Congress on Medical Physics and Biomedical Engineering 2018 : June 3–8, 2018, Prague, Czech Republic (Vol. 2)2018 / p. 237-240 https://doi.org/10.1007/978-981-10-9038-7_44 Conference Proceedings at Scopus Article at Scopus Article at WOS

Eesti teadlased loodavad panna putukrobotile pähe tehisaruRaik, Jaannovaator.err.ee2024 Eesti teadlased loodavad panna putukrobotile pähe tehisaru Эстонские ученые создают робота-насекомого с искусственным интеллектом

Eesti teaduse nähtamatud hiiglasedRaik, JaanTeadusmõte Eestis (X). Tehnikateadused. 3 : [artiklikogumik]2019 / lk. 161-168 : ill., fot https://www.ester.ee/record=b5208765*est

An efficient analog convolutional neural network hardware accelerator enabled by a novel memoryless architecture for insect-sized robotsDadras, Iman; Ahmadilivani, Mohammad Hasan; Banerji, Saoni; Raik, Jaan; Abloo, Alvo2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST) : Bremen, Germany : 08-10 June 20222022 / p. 1-6 https://doi.org/10.1109/MOCAST54814.2022.9837551

Efficient fault injection based on dynamic HDL slicing techniqueBagbaba, Ahmet Cagri; Jenihhin, Maksim; Raik, Jaan; Sauer, Christian2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019) : 1-3 July 2019, Greece2019 / p. 52-53 : ill https://doi.org/10.1109/IOLTS.2019.8854419

An efficient FPGA-based architecture for contractive autoencodersKerner, Madis; Tammemäe, Kalle; Raik, Jaan; Hollstein, Thomas2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 3 – 6 May 2020, Fayetteville, Arkansas : proceedings2020 / p. 230−230 https://doi.org/10.1109/FCCM48280.2020.00062.

Efficient hierarchical approach to test generation for digital systemsUbar, Raimund-Johannes; Raik, JaanIEEE ISQED 2000 : proceedings of the IEEE 2000 1st International Symposium on Quality Electronic Design : March 20-22, 2000, San Jose, California2000 / p. 189-195 : ill

Efficient single-pattern fault simulation on structurally synthesized BDDsRaik, Jaan; Ubar, Raimund-Johannes; Devadze, Sergei; Jutman, ArturDependable Computing - EDCC-5 : 5th European Dependable Computing Conference : Budapest, Hungary, April 20-22, 2005 : proceedings2005 / p. 332-344 : ill

E-learning environment for WEB-based study of testingUbar, Raimund-Johannes; Jutman, Artur; Raik, Jaan; Devadze, Sergei; Jenihhin, Maksim; Aleksejev, Igor; Tšepurov, Anton; Tšertov, Anton; Kostin, Sergei; Orasson, Elmet; Wuttke, Heinz-DietrichProceedings of the 8th European Workshop on Microelectronics Education : EWME 2010 : Darmstadt, Germany, 10-12 May 20102010 / p. 47-52 : ill

Embedded diagnosis in digital systemsUbar, Raimund-Johannes; Kostin, Sergei; Raik, Jaan2008 26th International Conference on Microelectronics : Niš, Serbia, 11-14 May 2008 : proceedings. Vol. 22008 / p. 421-424 : ill

Embedded fault diagnosis in digital systems with BISTUbar, Raimund-Johannes; Kostin, Sergei; Raik, JaanMicroprocessors and microsystems2008 / 5/6, p. 279-287 : ill

Energy-efficient multi-fragment Markov model guided online model-based testing for MPSoCVain, Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Apneet Kaur; Jenihhin, Maksim; Raik, Jaan; Nõmm, SvenGreen IT Engineering: Social, Business and Industrial Applications2019 / p. 273-297 https://doi.org/10.1007/978-3-030-00253-4_12 Article collection at Scopus Article at Scopus

Engineering of an effective automatic dynamic assertion mining platformGhasempouri, Tara; Malburg, Jan; Danese, Alessandro; Pravadelli, Graziano; Fey, Goerschwin; Raik, JaanVLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]2019 / p. 111-116 : ill https://doi.org/10.1109/VLSI-SoC.2019.8920331

Enhancing hierarchical ATPG with a functional fault model for multiplexers [Electronic resource]Raik, Jaan; Ubar, Raimund-Johannes7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems : April 18-21, 2004, Stará Lesná, Slovakia : proceedings2004 / p. 219-222 : ill. [CD-ROM]

Environment for fault simulation acceleration on FPGAEllervee, Peeter; Raik, Jaan; Tihhomirov, ValentinBEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia2004 / p. 217-220 : ill

Environment for FPGA-based fault emulationEllervee, Peeter; Raik, Jaan; Tammemäe, Kalle; Ubar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering2006 / 3-2, p. 323-335 : ill

Evaluating fault emulation on FPGAEllervee, Peeter; Raik, Jaan; Tihhomirov, Valentin; Tammemäe, KalleField-Programmable Logic and Applications : 14th International Conference, FPL 2004 : Antwerp, Belgium, August 30-September 1, 2004 : proceedings2004 / p. 354-363 : ill

Evolutionary approach to test generation for functional BISTSkobtsov, Y.A.; Ivanov, D.E.; Skobtsov, V.Y.; Ubar, Raimund-Johannes; Raik, JaanInformal Digest of Papers : 10 IEEE European Test Symposium : Tallinn, Estonia, May 22-25, 20052005 / p. 151-155 : ill https://artiklid.elnet.ee/record=b1018764*est

Exact parallel critical path fault tracing to speed-up fault simulation in sequential circuitsKõusaar, Jaak; Ubar, Raimund-Johannes; Kostin, Sergei; Devadze, Sergei; Raik, JaanInternational journal of microelectronics and computer science2018 / p. 9−18 https://ijmcs.dmcs.pl/web/guest/vol.-9-no.-1 https://ijmcs.dmcs.pl/documents/10630/345460/IJMCS_1_2018_2.pdf

Exact static compaction of independent test sequencesRaik, Jaan; Jutman, Artur; Ubar, Raimund-JohannesBEC 2002 : proceedings of the 8th Biennial Baltic Electronics Conference : October 6-9, 2002, Tallinn, Estonia2002 / p. 315-318 : ill

Exact static compaction of sequential circuit tests using branch-and-bound and search state registrationRaik, Jaan; Jutman, Artur; Ubar, Raimund-JohannesETW'02 : 7th IEEE European Test Workshop, Gorfu Greece, May 26-29, 2002 : informal digest2002 / p. 19-20

Experimental comparison of different diagnosis algorithms in the BIST environmentUbar, Raimund-Johannes; Kostin, Sergei; Raik, Jaan; Kruus, MargusProceedings of the 16th IASTED International Conference on Applied Simulation and Modelling : August 29-31, 2007, Palma de Mallorca, Spain2007 / p. 271-276 : ill

Exploiting high-level descriptions for circuits fault tolerance assessmentsBenso, A.; Prinetto, Paolo; Rebaudengo, M.; Sonza Reorda, Matteo; Raik, Jaan; Ubar, Raimund-Johannes1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, October 20-22, 19971997 / p. 212-216

Explorations in low area overhead DfT techniques for sequential BISTRaik, Jaan; Raidma, Rein; Ubar, Raimund-JohannesIEEE NORCHIP 2003 : 21 Norchip Conference : Riga, Latvia, 10-11 November 2003 : proceedings2003 / p. 220-223 : ill

Extended checkers for control part of routers in network-on-chipsHariharan, Ranganathan; Niazmand, Behrad; Hollstein, Thomas; Raik, Jaan; Jervan, GertMEDIAN 2015 : the 4th Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : March 13, 2015, Grenoble, France2015 / p. 36-39 : ill

Extended checkers for logic-based distributed routing in network-on-chipsNiazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, JaanProceedings of the 8th Annual Conference of the Estonian National Doctoral School in Information and Communication Technologies : December 5-6, 2014, Rakvere2014 / p. 83-86 : ill

Extended checkers for logic-based distributed routing in network-on-chipsNiazmand, Behrad; Hariharan, Ranganathan; Govind, Vineeth; Jervan, Gert; Hollstein, Thomas; Raik, JaanBEC 2014 : 2014 14th Biennial Baltic Electronics Conference : proceedings of the 14th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 6-8, 2014, Tallinn, Estonia2014 / p. 77-80 : ill

Extensible open-source framework for translating RTL VHDL IP cores to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, JaanProceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 8-10, 2013, Karlovy Vary, Czech Republic2013 / p. 112-115

Fast and efficient static compaction of test sequences based on greedy algorithmsRaik, Jaan; Jutman, Artur; Ubar, Raimund-JohannesIEEE Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS 2001 : Fourth International Workshop on IEEE Design and Diagnostics of Electronic Circuits and Systems : Györ, Hungary, April 18-20, 20012001 / p. 117-122

Fast and efficient static compaction of test sequences using bipartite graph representationsMarkus, Antti; Raik, Jaan; Ubar, Raimund-JohannesECS'99 : proceedings of the 2nd Electronic Circuits and Systems Conference : September 6-8, 1999, Bratislava, Slovakia1999 / p. 17-20

Fast fault emulation for synchronous sequential circuitsRaik, Jaan; Ellervee, Peeter; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings of East–West Design & Test Workshop (EWDTW’04) : Yalta, Alushta, Crimea, Ukraine, September 23-26, 20042004 / p. 35-40 https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=a6eb712498a5f23db3f95ad66bada257c21e96f0

Fast fault simulation for extended class of faults in scan-path circuitsUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, ArturProceedings : Fifth IEEE International Symposium on Electronic Design, Test and Applications : DELTA 2010 : 13-15 January 2010, Ho Chi Minh City, Vietnam2010 / p. 14-19

Fast identification of true critical paths in sequential circuitsUbar, Raimund-Johannes; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Jürimägi, LembitMicroelectronics reliability2018 / p. 252-261 : ill https://doi.org/10.1016/j.microrel.2017.11.027 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Fast RTL fault simulation using decision diagrams and bitwise set operationsReinsalu, Uljana; Raik, Jaan; Ubar, Raimund-Johannes; Ellervee, Peeter2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : 3-5 October 2011, Vancouver, Canada2011 / p. 164-170

Fast static compaction of test sequences using implications and greedy searchRaik, Jaan; Jutman, Artur; Ubar, Raimund-JohannesETW 2001 : IEEE European Test Workshop : Stockholm, May 29 June 1, 2001 : informal digest2001 / p. 207-209 : ill

Fast static compaction of tests composed of independent sequences : basic properties and comparison of methodsRaik, Jaan; Jutman, Artur; Ubar, Raimund-JohannesThe 9th IEEE International Conference on Electronics, Circuits and Systems : ICECS 2002 : September 15-18, 2002, Dubrovnik, Croatia. Volume II2002 / p. 445-448 : ill http://dx.doi.org/10.1109/ICECS.2002.1046190 https://ieeexplore.ieee.org/document/1046190

Fast test pattern generation for sequential circuits using decision diagram representationsRaik, Jaan; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications (JETTA)2000 / 3, p. 213-226 : ill https://link.springer.com/article/10.1023/A:1008335130158

Fault collapsing in digital circuits using fast fault dominance and equivalence analysis with SSBDDsUbar, Raimund-Johannes; Jürimägi, Lembit; Orasson, Elmet; Raik, JaanVLSI-SoC : Design for Reliability, Security, and Low Power : 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 Daejeon, Korea, October 5-7, 2015 : revised selected papers2016 / p. 23-45 : ill http://dx.doi.org/10.1007/978-3-319-46097-0_2

Fault collapsing with linear complexity in digital circuitsUbar, Raimund-Johannes; Mironov, Dmitri; Raik, Jaan; Jutman, ArturProceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010) : 30 May - 2 June 2010, Paris, France2010 / p. 653-656 : ill

Fault diagnosis in integrated circuits with BISTUbar, Raimund-Johannes; Kostin, Sergei; Raik, Jaan; Evartson, Teet; Lensen, Harri10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007 : 29-31 August 2007, Lübeck, Germany : proceedings2007 / p. 604-610 : ill http://dx.doi.org/10.1109/DSD.2007.4341530

Fault diagnosis in the BIST environment based on bisection of detected faultsUbar, Raimund-Johannes; Kostin, Sergei; Raik, JaanLATW2007 : 8th IEEE Latin-American Test Workshop : March 11-14, 2007, Cuzco, Peru2007 / [6] p. : ill

Fault emulation on FPGA : a feasibility studyEllervee, Peeter; Raik, Jaan; Tihhomirov, ValentinIEEE NORCHIP 2003 : 21 Norchip Conference : Riga, Latvia, 10-11 November 2003 : proceedings2003 / p. 92-95 : ill

Fault model and test synthesis for RISC-processorsUbar, Raimund-Johannes; Markus, Antti; Jervan, Gert; Raik, JaanBEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 229-232: ill

Fault oriented test pattern generation for sequential circuits using genetic algorithmsIvask, Eero; Raik, Jaan; Ubar, Raimund-JohannesIEEE European Test Workshop2000 / p. 319-320

Fault oriented test pattern generation for sequential circuits using Genetic AlgorithmsIvask, Eero; Raik, Jaan; Ubar, Raimund-JohannesThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 129-132 : ill

Fault simulation and code coverage analysis of RTL designs using high-level decision diagrams = Rikete simuleerimine ja koodikatte analüüs register-siirde tasemel kasutades kõrgtaseme otsustusdiagrammeReinsalu, Uljana2013 https://www.ester.ee/record=b2963595*est

Fault simulation with parallel critical path tracing for combinational circuits using structurally synthesized BDDsDevadze, Sergei; Raik, Jaan; Jutman, Artur; Ubar, Raimund-Johannes7th IEEE Latin American Test Workshop LATW'06 : Buenos Aires, Argentina, March 26th-29th, 2006 : proceedings2006 / p. 97-102 : ill

Fault-aware performance assessment approach for embedded networksMalburg, Jan; Janson, Karl; Raik, Jaan; Dannemann, Frank2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Cluj-Napoca, Romania : proceedings2019 / 4 p. : ill https://doi.org/10.1109/DDECS.2019.8724670

Fault-resilient NoC router with transparent resource allocationPutkaradze, Tsotne; Azad, Siavoosh Payandeh; Niazmand, Behrad; Raik, Jaan; Jervan, Gert12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC2017), July 12-14, 2017, Madrid, Spain : proceedings2017 / 8 p. : ill https://doi.org/10.1109/ReCoSoC.2017.8016161 https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8016161

Feasibility of structurally synthesized BDD models for test generationRaik, Jaan; Ubar, Raimund-JohannesProceedings of the IEEE European Test Workshop, Barcelona, Spain, May 27-29, 19981998 / p. 145-146

FoREnSiC– an automatic debugging environment for C programsBloem, Roderick; Raik, Jaan; Repinski, UrmasEighth Haifa Verification Conference : HVC 2012 : November 6-8, Haifa, Israel : [proceedings]2012 / p. 1-6 : ill

Formal verification and error correction on high-level decision diagrams = Formaalne verifitseerimine ja vigade parandamine kõrgtasemelistel otsustusdiagrammidelKarputkin, Anton2012

FP7 collaborative research project DIAMOND : diagnosis, error modeling and correction for reliable systems designRaik, JaanProceedings : 2012 17th IEEE European Test Symposium (ETS) : May 28th–June 1st, 2012, Annecy, France2012 / 1 p https://ieeexplore.ieee.org/document/6233052

FP7 DIAMOND : design error diagnosis and correction success storiesRaik, Jaan; Jenihhin, Maksim; Könighofer, RobertEuropean Test Symposium (ETS), 2013, Avignon, France2013 / p. 1-6

FPGA based fault emulation of synchronous sequential circuitsEllervee, Peeter; Raik, Jaan; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings [of] 22nd NORCHIP Conference : Oslo, Norway, 8-9 November 20042004 / p. 59-62 https://ieeexplore.ieee.org/abstract/document/1423822

FPGA design flow with automated test generationElst, G.; Diener, Karl-Heinz; Ivask, Eero; Raik, Jaan; Ubar, Raimund-JohannesProc. of German 11th Workshop on Test Technology and Reliability of Circuits and Systems : Potsdam, 19991999 / p. 120-123

FPGA-based fault emulation of synchronous sequential circuitsEllervee, Peeter; Raik, Jaan; Tammemäe, Kalle; Ubar, Raimund-JohannesIET computers and digital techniques2007 / 2, p. 70-76 : ill https://ieeexplore.ieee.org/abstract/document/1423822

A framework for area-efficient concurrent online checkers designSaltarelli, Pietro; Niazmand, Behrad; Hariharan, Ranganathan; Raik, Jaan; Jervan, Gert; Hollstein, ThomasMEDIAN Finale : Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : November 10-11, 2015, Tallinn, Estonia2015 / p. 64-69 : ill

A framework for combining concurrent checking and online embedded test for low-latency fault detection in NoC routersSaltarelli, Pietro; Niazmand, Behrad; Raik, Jaan; Govind, Vineeth; Hollstein, Thomas; Jervan, Gert; Hariharan, RanganathanNOCS '15 : International Symposium on Networks-on-Chip : Vancouver, BC, Canada, September 28-30, 20152015 / [8] p. : ill http://dx.doi.org/10.1145/2786572.2788713

A framework for comprehensive automated evaluation of concurrent online checkersSaltarelli, Pietro; Niazmand, Behrad; Raik, Jaan; Hariharan, Ranganathan; Jervan, Gert; Hollstein, ThomasEuromicro Conference on Digital System Design : DSD 2015 : 26-28 August 2015, Funchal, Madeira, Portugal : proceedings2015 / p. 288-292 : ill http://dx.doi.org/10.1109/DSD.2015.15

From online fault detection to fault management in network-on-chips : a ground-up approachAzad, Siavoosh Payandeh; Niazmand, Behrad; Janson, Karl; Nevin, George; Oyeniran, Adeboye Stephen; Putkaradze, Tsotne; Apneet Kaur; Raik, Jaan; Jervan, Gert; Ubar, Raimund-Johannes; Hollstein, ThomasProceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany2017 / p. 48-53 : ill https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553

From RTL liveness assertions to cost-effective hardware checkersHariharan, Ranganathan; Ghasempouri, Tara; Niazmand, Behrad; Raik, JaanXXXIII Conference on Design of Circuits and Integrated Systems (DCIS) : proceedings2018 / 6 p. : ill https://doi.org/10.1109/DCIS.2018.8681487

FSMD RTL design manipulation for clock interface abstractionAbrar, Syed Saif; Jenihhin, Maksim; Raik, Jaan2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI) : 10-13 August 2015, Kerala, India2015 / p. 463-468 : ill http://dx.doi.org/10.1109/ICACCI.2015.7275652

Functional self-test of high-performance pipe-lined signal processing architecturesGorev, Maksim; Ubar, Raimund-Johannes; Ellervee, Peeter; Devadze, Sergei; Raik, Jaan; Min, MartMicroprocessors and microsystems2015 / p. 909-918 : ill http://dx.doi.org/10.1016/j.micpro.2014.11.002

Functional test generation for finite state machinesUbar, Raimund-Johannes; Brik, Marina; Jutman, Artur; Raik, Jaan; Bengtsson, Tomas; Kumar, ShashiBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 205-208 : ill

GA-based test generation for sequential circuitsBrik, Marina; Raik, Jaan; Ubar, Raimund-Johannes; Ivask, EeroProceedings of East–West Design & Test Workshop (EWDTW’04) : Yalta, Alushta, Crimea, Ukraine, September 23-26, 20042004 / p. 30-34

Gate-level modelling of NBTI-induced delays under process variationsCopetti, Thiago; Cardoso Medeiros, Guilherme; Bolzani Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-JohannesLATS 2016 : 17th IEEE Latin-American Test Symposium, Foz do Iguacu, Brazil, 6th-9th April 20162016 / p. 75-80 : ill http://dx.doi.org/10.1109/LATW.2016.7483343

Generating directed tests for C programs using RTL ATPGRaik, Jaan; Drenkhan, Tiia; Jenihhin, Maksim; Viilukas, Taavi; Karputkin, Anton; Tšepurov, Anton; Ubar, Raimund-JohannesProceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)2012 / p. 1-6

Generic interconnect BIST for Network-on-ChipJutman, Artur; Ubar, Raimund-Johannes; Raik, JaanDDECS : 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems : April 13-16, 2005, Sopron, Hungary : proceedings2005 / p. 224-227 : ill

Greedy alternative for the static compaction of sequential circuit test sequencesRaik, JaanThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 133-136 : ill

Handbook of testing electronic systemsNovak, Ondrej; Gramatova, Elena; Ubar, Raimund-Johannes; Jutman, Artur; Raik, Jaan2005 https://www.ester.ee/record=b2102523*est

Handling of SETs on NoC links by exploitation of inherent redundancy in circular input buffers [Online resource]Janson, Karl; Pihlak, Rene; Azad, Siavoosh Payandeh; Niazmand, Behrad; Jervan, Gert; Raik, JaanBEC 2018 : 2018 16th Biennial Baltic Electronics Conference (BEC) : proceedings of the 16th Biennial Baltic Electronics Conference, October 8-10, 20182018 / 4 p.: ill https://doi.org/10.1109/BEC.2018.8600989

Hardware modeling for design verification and debug = Riistvara modelleerimine disaini verifitseerimise ja silumise jaoksTšepurov, Anton2013 https://www.ester.ee/record=b2963501*est

Hierarchical analysis of short defects between metal lines in CMOS ICPleskacz, Witold A.; Jenihhin, Maksim; Raik, Jaan; Rakowski, Michal; Ubar, Raimund-Johannes; Kuzmicz, WieslawProceedings : 11th EUROMICRO Conference on Digital System Design : Architectures, Methods and Tools : (DSD 2008) : September 3-5, 2008, Parma, Italy2008 / p. 729-734 : ill

A hierarchical approach for devising area efficient concurrent online checkersNiazmand, Behrad; Azad, Siavoosh Payandeh; Ghasempouri, Tara; Raik, Jaan; Jervan, GertProceedings 2nd IEEE International Test Conference in Asia : ITC-Asia 2018, 15-17 August 2018, Harbin, China2018 / p. 139-144 : ill https://doi.org/10.1109/ITC-Asia.2018.00034

A hierarchical automatic test pattern generator based on using alternative graphsBrik, Marina; Jervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 4th International Workshop Mixed Design of Integrated Circuits and Systems : MIXDES'97 : Poznan, Poland, 12-14 June 19971997 / p. 415-420

Hierarchical calculation of malicious faults for evaluating the fault-toleranceUbar, Raimund-Johannes; Devadze, Sergei; Jenihhin, Maksim; Raik, Jaan; Jervan, Gert; Ellervee, PeeterProceedings : Fourth IEEE International Symposium on Electronic Design, Test and Applications : [DELTA 2008] : 23-25 January 2008, Hong Kong, SAR, China2008 / p. 222-227 : ill

Hierarchical defect level test quality analysisBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesVILAB User Forum2000 / [11] p

Hierarchical defect-oriented fault simulation for digital circuitsBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE European Test Workshop : 23-26 May 2000, Cascais, Portugal : ETW 2000 : proceedings2000 / p. 69-74 : ill

Hierarchical defect-oriented fault simulation for digital circuitsBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE European Test Workshop2000 / p. 151-156 https://ieeexplore.ieee.org/document/873781

Hierarchical fault simulation for finite state machinesBrik, Marina; Raik, Jaan; Ubar, Raimund-JohannesThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 145-148 : ill

Hierarchical fault simulation in digital systemsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaInternational Symposium on Signals, Circuits and Systems : SCS 2001 : July 10-11, 2001, Iasi, Romania : proceedings2001 / p. 181-184 : ill

Hierarchical identification of NBTI-critical gates in nanoscale logicKostin, Sergei; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, MaksimLATW2014 : 15th IEEE Latin-American Test Workshop : Fortaleza, Brazil, March 12th-15th, 20142014 / [6] p. : ill

Hierarchical identification of untestable faults in sequential circuitsRaik, Jaan; Ubar, Raimund-Johannes; Krivenko, Anna; Kruus, Margus10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007 : 29-31 August 2007, Lübeck, Germany : proceedings2007 / p. 668-671 : ill http://dx.doi.org/10.1109/DSD.2007.4341539

Hierarchical physical defect reasoning in digital circuitsKostin, Sergei; Ubar, Raimund-Johannes; Raik, Jaan; Brik, MarinaEstonian journal of engineering2011 / 3, p. 185-200

Hierarchical test generation for combinational circuits with real defects coverageCibakova, Tatiana; Fischerova, Maria; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesMicroelectronics reliability2002 / p. 1141-1149 : ill

Hierarchical test generation for complex digital systems with control and data processing partsUbar, Raimund-Johannes; Raik, Jaan"Test, Assembly and Packaging" : SEMICON Technical Symposium : Singapur, May 3-6, 19991999 / p. 43-52

Hierarchical test generation for digital circuits represented by Decision Diagrams : thesis on informatics and system engineeringRaik, Jaan2001 https://www.ester.ee/record=b1578107*est

Hierarchical test generation for digital systemsBrik, Marina; Jervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesMixed design of integrated circuits and systems1998 / p. 131-136: ill

Hierarchical test generation for digital systems based on combining bottom-up and top-down approachesRaik, Jaan; Ubar, Raimund-JohannesWorld Multiconference on Systemics, Cybernetics and Informatics, July 12-16, 1998, Orlando, Florida : proceedings. Vol. 11998 / p. 374-381: ill

Hierarchical test generation with multi-level decision diagram modelsJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 7th IEEE North Atlantic Test Workshop, West Greenwich RI, USA, May 28-29, 19981998 / p. 26-33

Hierarchical test generation. SEMI show slidesUbar, Raimund-Johannes; Raik, Jaan"Test, Assembly and Packaging" : SEMICON Technical Symposium : Singapur, May 3-6, 19991999 / p. 53-64

Hierarchical test pattern generation and untestability identification techniques for synchronous sequential circuits = Hierarhilised testintegreerimise ja mittetestitavuse identifitseerimise meetodid sünkroonsetele järjestikskeemideleRannaste, Anna2010 https://www.ester.ee/record=b2637391*est

Hierarchical timing-critical paths analysis in sequential circuitsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Kostin, Sergei2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain2018 / 6 p. : ill https://doi.org/10.1109/PATMOS.2018.8464176

High level fault modeling in digital systemsUbar, Raimund-Johannes; Aarna, Margit; Brik, Marina; Raik, JaanSynergies between Information and Automation : 49. Internationales Wissenschaftliches Kolloquium, 27.-30.9.2004, Technische Universität Ilmenau, Germany. Volume 22004 / p. 486-491

High quality test generation for digital systemsUbar, Raimund-Johannes; Aarna, Margit; Kruus, Helena; Raik, JaanRomanian journal of information science and technology2005 / 1, p. 73-84 : ill

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan2019 IEEE European Test Symposium (ETS) : ETS 2019, May 27-31, 2019, Baden-Baden, Germany : Proceedings2019 / 6 p. : ill https://doi.org/10.1109/ETS.2019.8791526

High-level combined deterministic and pseudo-exhuastive test generation for RISC processorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Gürsoy, Cemil Cem; Raik, Jaan2019 IEEE European Test Symposium (ETS) : proceedings2019 / 6 p. : ill https://doi.org/10.1109/ETS.2019.8791526

High-level decision diagram based fault models for targeting FSMsRaik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi9th EUROMICRO Conference on Digital Systems Design : Architectures, Methods and Tools (DSD 2006) : 30 August 2006-1 September 2006, Cavtat near Dubrovnik, Croatia : proceedings2006 / p. 353-358 : ill http://dx.doi.org/10.1109/DSD.2006.60

High-Level Decision Diagram manipulations for code coverage analysisMinakova, Karina; Reinsalu, Uljana; Tšepurov, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Ellervee, PeeterBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 207-210 : ill

High-level decision diagram simulation for diagnosis and soft-error analysisRaik, Jaan; Repinski, Urmas; Jenihhin, Maksim; Chepurov, AntonDesign and test technology for dependable systems-on-chip2011 / p. 294-309 : ill

High-level decision diagrams based coverage metrics for verification and testJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesLATW 2009 : 10th IEEE Latin American Test Workshop : Buzios, Rio de Janero, Brazil, March 2-5, 20092009 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2009.4813792

High-level decision diagrams for improving simulation performance of digital systemsUbar, Raimund-Johannes; Raik, Jaan; Morawiec, AdamSCI 2000 : World Multiconference on Systemics, Cybernetics and Informatics : July 23-26, 2000, Orlando, Florida, USA : proceedings. Volume IX, Industrial Systems2000 / p. 62-67 : ill

High-level design error diagnosis using backtrace on decision diagramsRaik, Jaan; Repinski, Urmas; Ubar, Raimund-Johannes; Jenihhin, Maksim; Tšepurov, Anton28th Norchip Conference : Tampere, Finland, 15-16 November 2010 : conference program and papers2010 / [4] p. : ill http://dx.doi.org/10.1109/NORCHIP.2010.5669486

High-level fault diagnosis in RISC processors with Implementation-Independent Functional TestOyeniran, Adeboye Stephen; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) : Nicosia, Cyprus : 04-06 July 20222022 / p. 32-37 https://doi.org/10.1109/ISVLSI54635.2022.00019

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanJournal of electronic testing : theory and applications2020 / p. 87-103 https://doi.org/10.1007/s10836-020-05856-7

High-level intellectual property obfuscation via decoy constantsAksoy, Levent; Nguyen, Quang-Linh; Almeida, Felipe; Raik, Jaan; Flottes, Marie-Lise; Dupuis, Sophie; Pagliarini, Samuel Nascimento2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), 28-30 June 20212021 / p. 1-7 https://doi.org/10.1109/IOLTS52814.2021.9486714

High-level path activation technique to speed up sequential circuit test generationRaik, Jaan; Ubar, Raimund-JohannesEuropean Test Workshop 1999 : proceedings, May 25-28, 1999, Constance, Germany1999 / p. 84-89 : ill

High-level synthesis and test in the MOSCITO-based virtual laboratorySchneider, Andre; Diener, Karl-Heinz; Jervan, Gert; Peng, Z.; Raik, Jaan; Ubar, Raimund-Johannes; Hollstein, Thomas; Glesner, M.BEC 2002 : proceedings of the 8th Biennial Baltic Electronics Conference : October 6-9, 2002, Tallinn, Estonia2002 / p. 287-290 : ill

High-level test generation for processing elements in many-core systemsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Azad, Siavoosh Payandeh; Raik, Jaan12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC2017), July 12-14, 2017, Madrid, Spain : proceedings2017 / 8 p. : ill http://dx.doi.org/10.1109/ReCoSoC.2017.8016156

High-level test synthesis with hierarchical test generationJervan, Gert; Eles, Petru; Peng, Zebo; Raik, Jaan; Ubar, Raimund-Johannes17th NORCHIP Conference : Oslo, Norway, 8-9 November 1999 : proceedings1999 / p. 291-296

Holistic approach for Fault-Tolerant Network-on-Chip based many-core systems [Online resource]Azad, Siavoosh Payandeh; Niazmand, Behrad; Raik, Jaan; Jervan, Gert; Hollstein, ThomasarXiv.org2016 / [8] p. : ill

How to generate high quality tests for digital systemsUbar, Raimund-Johannes; Aarna, Margit; Kruus, Helena; Raik, Jaan2004 International Semiconductor Conference : 27th edition, October 4-6, 2004, Sinaia, Romania : CAS 2004 proceedings. Volume 22004 / p. 459-462 : ill http://dx.doi.org/10.1109/SMICND.2004.1403048

How to prove that a circuit is fault-free?Ubar, Raimund-Johannes; Kostin, Sergei; Raik, JaanProceedings : 15th Euromicro Conference on Digital System Design DSD 2012 : 5-8 September 2012, Cesme, Izmir, Turkey2012 / p. 427-430 : ill

"Hullkoer" käis Tehnikaülikoolis : [TTÜs pidas loengu Linux International'i direktor John "Maddog" Hall]Kruus, Margus; Raik, JaanMente et Manu2002 / lk. 3 : fot https://www.ester.ee/record=b1242496*est

"Hullkoer" käis Tehnikaülikoolis : [TTÜs pidas loengu Linux International'i direktor John "Maddog" Hall]Kruus, Margus; Raik, JaanArvutikasutaja2002 / lk. 5 : fot

Hybrid protection of digital FIR filtersAksoy, Levent; Nguyen, Quang-Linh; Almeida, Felipe; Raik, Jaan; Flottes, Marie-Lise; Dupuis, Sophie; Pagliarini, Samuel NascimentoIEEE transactions on Very Large Scale Integration (VLSI) Systems2023 / p. 812-825 : ill https://doi.org/10.1109/TVLSI.2023.3253641 Journal metrics at Scopus

HyFBIST : hybrid functional built-in self-test in microprogrammed data-paths of digital systemsUbar, Raimund-Johannes; Mazurova, Natalja; Smahtina, Julia; Orasson, Elmet; Raik, JaanProceedings of the 11th International Conference : Mixed Design of Integrated Circuits and Systems : MIXDES 2004 : Szczecin, Poland, 24-26 June 20042004 / p. 497-502 : ill

Identification and rejuvenation of NBTI-critical logic paths in nanoscale circuitsJenihhin, Maksim; Squillero, Giovanni; Tihhomirov, Valentin; Kostin, Sergei; Raik, Jaan; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications (JETTA)2016 / p. 273-289 : ill http://dx.doi.org/10.1007/s10836-016-5589-x

Identifying NBTI-critical paths in nanoscale logicUbar, Raimund-Johannes; Vargas, Fabian; Jenihhin, Maksim; Raik, Jaan; Kostin, Sergei; Bolzani Poehls, Leticia16th Euromicro Conference series on Digital System Design : DSD 2013 : proceedings : 4-6 September 2013, Santander, Spain2013 / p. 136-141 : ill

Identifying untestable faults in sequential circuits using test path constraintsViilukas, Taavi; Karputkin, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Fujiwara, HideoJournal of electronic testing : theory and applications (JETTA)2012 / p. 511-521 : ill

IEEE Euroopa 10. Testisümpoosion Tallinnas : [21.-26. maini 2005 hotellis "Olümpia" ja konverentsi õppeseminarid TTÜ Energeetikamajas]Raik, JaanMente et Manu2006 / 18. jaan., lk. 5 https://www.ester.ee/record=b1242496*est

IEEE European Test Symposium (ETS)Eggersgluss, Stephan; Hamdioui, Said; Jutman, Artur; Michael, Maria K.; Raik, Jaan2019 IEEE International Test Conference (ITC)2019 / 4 p https://doi.org/10.1109/ITC44170.2019.9000148 Conference proceeding at Scopus Article at Scopus Article at WOS

IMMizer : an innovative cost-effective method for minimizing assertion setsHeidari Iman, Mohammad Reza; Raik, Jaan; Jervan, Gert; Ghasempouri, TaraProceedings - 2022 25th Euromicro Conference on Digital System Design, DSD 20222022 / p. 671 - 678 https://doi.org/10.1109/DSD57027.2022.00095 Article at Scopus Article at WOS

Implementation-independent functional test for transition delay faults in microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan2020 23rd Euromicro Conference on Digital System Design (DSD), 26-28 August 2020, Kranj, Slovenia2020 / p. 646-650 https://doi.org/10.1109/DSD51259.2020.00105

Implementation-independent functional test generation for RISC microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]2019 / p. 82-87 : ill https://doi.org/10.1109/VLSI-SoC.2019.8920323

Implementation-independent test generation for a large class of faults in RISC processor modulesJenihhin, Maksim; Oyeniran, Adeboye Stephen; Raik, Jaan; Ubar, Raimund-Johannes24th Euromicro Conference on Digital System Design (DSD)2021 https://doi.org/10.1109/DSD53832.2021.00090

Improved fault emulation for synchronous sequential circuitsRaik, Jaan; Ellervee, Peeter; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 72-78 : ill

Integrated modelling, fault management, verification and reliable design environment for cyber-physical systemsRaik, Jaan; Rauwerda, Gerard; Zhao, Yong; Shibin, KonstantinMEDIAN Finale : Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : November 10-11, 2015, Tallinn, Estonia2015 / p. 74

Integration of digital test tools to the internet-based environment MOSCITOSchneider, Andre; Diener, Karl-Heinz; Elst, Günter; Ivask, Eero; Raik, Jaan; Ubar, Raimund-JohannesSCI 2003 : the 7th World Multiconference on Systemics, Cybernetics and Informatics : July 27-30, 2003, Orlando, Florida, USA : proceedings. Volume VIII, Applications of Informatics and Cybernetics in Science and Engineering2003 / p. 136-141 : ill

Interactive presentation abstract : automated correction of design errors by edge redirection on high-level decision diagrams [Electronic resource]Karputkin, Anton; Ubar, Raimund-Johannes; Tombak, Mati; Raik, JaanIEEE International High Level Design Validation and Test Workshop (HLDVT'11), November 9-11, 2011, Napa Valley, CA2011 / p. 83 : ill. [CD-ROM] http://doi.ieeecomputersociety.org/10.1109/HLDVT.2011.6113980

Internet based test generation and fault simulationIvask, Eero; Ubar, Raimund-Johannes; Raik, Jaan; Schneider, AndreIEEE Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS 2001 : Fourth International Workshop on IEEE Design and Diagnostics of Electronic Circuits and Systems : Györ, Hungary, April 18-20, 20012001 / p. 57-60 : ill

Internet-based collaborative test generation with MOSCITO [Electronic resource]Schneider, Andre; Ivask, Eero; Miklos, P.; Raik, Jaan; Diener, Karl-Heinz; Ubar, Raimund-Johannes; Cibakova, Tatiana; Gramatova, ElenaSIGDA publications on CD-ROM : DATE'02 : Design, Automation and Test in Europe, Paris, France, March 4-8, 20022002 / [6] p. [CD-ROM]

Internet-based software for teaching test of digital circuitsUbar, Raimund-Johannes; Jutman, Artur; Orasson, Elmet; Raik, Jaan; Evartson, Teet; Wuttke, Heinz-DietrichMicroelectronics education : proceedings of the 4th European Workshop on Microelectronics Education : EWME 2002, Spain, May 23-24, 20022002 / p. 317-320 : ill

Internet-based testability-driven test generation in the virtual environment MOSCITOSchneider, Andre; Diener, Karl-Heinz; Elst, G.; Ivask, Eero; Raik, Jaan; Ubar, Raimund-JohannesInternational Federation for Information Processing IFIP : International Workshop on IP-Based SoC Design 2002 : proceedings : Grenoble, October 30-31, 20022002 / p. 357-362 : ill http://publica.fraunhofer.de/dokumente/N-287433.html

Investigations of the diagnosibility of digital networks with BISTUbar, Raimund-Johannes; Kostin, Sergei; Raik, Jaan10th IEEE Latin American Test Workshop : 2-5 March 2009, Brazil2009 / [6] p. : ill

Jaan Raik : müütidest Eesti elektroonikatööstuse väljavaadete ümberRaik, Jaanerr.ee2022 Jaan Raik: müütidest Eesti elektroonikatööstuse väljavaadete ümber

Jaan Raik : Nurkse juhtumist ilma paranoiata [Võrguväljaanne]Raik, Jaanerr.ee2019 / fot Jaan Raik: Nurkse juhtumist ilma paranoiata

Jaan Raik : valedega "korruptsiooni" vastu [Võrguväljaanne]Raik, Jaanerr.ee2020 / fot Jaan Raik: valedega "korruptsiooni" vastu vaata ka: Keegan McBride: vastukaja artiklile "Valedega "korruptsiooni" vastu" (err.ee 24.01.2020)

Jaan Raik: kiibidisain aitaks saada Eestil jõukaks tehnoloogiamaaksMaidla, Margusnovaator.err.ee2023

Kakskümmend aastat hiljem : [vestlus arvutisüsteemide dignostika ja verifitseerimise õppetooli professori Jaan Raikiga]Raik, JaanMente et Manu2013 / lk. 10-12 : fot https://www.ester.ee/record=b1242496*est

Kiibikriis: kas maailmalõpp või Eesti võimalus?Raik, JaanPostimees2022 / Lk. 12 https://dea.digar.ee/article/postimees/2021/12/14/12.4

Kuidas teemant tehnikaülikooli tuliRaik, JaanTallinna Tehnikaülikooli aastaraamat 20092010 / lk. 40-43 : ill

Kuidas testida arvutivõrku ränikiibilRaik, Jaan; Govind, VineethA & A2010 / 4, lk. 35-37 https://artiklid.elnet.ee/record=b2286479*est

Layout to logic defect analysis for hierarchical test generationJenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Pleskacz, Witold A.; Rakowski, MichalProceedings of the 2007 IEEE Workshop on Design and Diagnostic Circuits and Systems : April 11-13, 2007, Krakow, Poland2007 / p. 35-40 : ill http://dx.doi.org/10.1109/DDECS.2007.4295251

LiD-CAT: A lightweight detector for cache ATtacksReinbrecht, Cezar; Hamdioui, Said; Taouil, Mottaqiallah; Niazmand, Behrad; Ghasempouri, Tara; Raik, Jaan; Sepulveda, Johanna2020 IEEE European Test Symposium (ETS) : ETS 2020, May 25-29, 2020
Tallinn, Estonia : proceedings2020 / 6 p. : ill https://doi.org/10.1109/ETS48528.2020.9131603

Linear algorithms for recognizing and parsing superpositional graphsPeder, Ahti; Nestra, Härmel; Raik, Jaan; Tombak, Mati; Ubar, Raimund-JohannesFacta Universitatis [Niš]. Series electronics and energetics2011 / p. 325-339 : ill http://dx.doi.org/10.2298/FUEE1103325P

Linear algorithms for testing superpositional graphsPeder, Ahti; Nestra, Härmel; Raik, Jaan; Tombak, Mati; Ubar, Raimund-JohannesProceedings of the Reed-Muller 2011 Workshop : May 25-26, 2011, Tuusula, Finland2011 / p. 111-118 : ill

Localization of bugs in processor designs using zamiaCAD frameworkTšepurov, Anton; Tihhomirov, Valentin; Jenihhin, Maksim; Raik, Jaan13th International Workshop on Microprocessor Test and Verification (MTV 2012) Common Challenges and Solutions : Austin, USA, December 10–12, 20122012 / p. 1-6

Logic simulation and fault collapsing with shared structurally synthesized BDDsMironov, Dmitri; Ubar, Raimund-Johannes; Raik, Jaan2014 19th IEEE European Test Symposium (ETS) : May 26th-30th, 2014, Paderborn, Germany : proceedings2014 / [2] p. : ill

Logic-based implementation of fault-tolerant routing in 3D Network-on-ChipsNiazmand, Behrad; Azad, Siavoosh Payandeh; Flich, Jose; Raik, Jaan; Jervan, Gert; Hollstein, Thomas2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS) : Nara, Japan, 31 August - 2 September 20162016 / [8] p. : ill https://doi.org/10.1109/NOCS.2016.7579317

Low-area boundary BIST architecture for mesh-like network-on-chipRaik, Jaan; Govind, VineethProceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 18-20, 2012 Tallinn, Estonia2012 / p. 95-100 : ill

Low-cost CAD software for teaching digital testUbar, Raimund-Johannes; Raik, Jaan; Paomets, PriiduFirst European Workshop on Microelectronics Education, Villard de Lans, France, February 5-6, 1996 : proceedings1996 / p. 48

Low-cost CAD system for teaching digital testUbar, Raimund-Johannes; Raik, Jaan; Paomets, Priidu; Ivask, Eero; Jervan, Gert; Markus, AnttiMicroelectronics education : proceedings of the European Workshop, Grenoble, France, 5-6 Feb 19961996 / p. 185-188

Macro level defect-oriented diagnosability of digital circuitsKostin, Sergei; Ubar, Raimund-Johannes; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / lk. 53-56 : ill

Macro level defect-oriented diagnosability of digital circuitsKostin, Sergei; Ubar, Raimund-Johannes; Raik, JaanBEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia2010 / p. 149-152 : ill

Measuring and identifying aging-critical paths in FPGAsPfeifer, Petr; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Pliva, ZdenekMEDIAN 2015 : the 4th Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : March 13, 2015, Grenoble, France2015 / p. 56-61 : ill

A methodology for automated mining of compact and accurate assertion setsHeidari Iman, Mohammadreza; Raik, Jaan; Jenihhin, Maksim; Jervan, Gert; Ghasempouri, Tara2021 IEEE Nordic Circuits and Systems Conference (NorCAS) : Oslo, Norway, October 26-272021 / 7 p. : ill https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9599865 https://doi.org/10.1109/NorCAS53631.2021.9599865

Methods for improving the accuracy and efficiency of fault simulation in digital systems = Meetodid digitaalsüsteemide rikete simuleerimise täpsuse ja efektiivsuse tõstmiseksKõusaar, Jaak2019 https://digi.lib.ttu.ee/i/?11667

Mikk Raud: Eestil on aeg oma kiibipotentsiaal ellu äratadaArjakas, Merilidiplomaatia.ee2023

Mikroelektroonika kiipide testimise tarkvara turbo-tester : kommentaar Eesti Teaduste Akadeemia Bernhard Schmidti preemia pälvinud tööleRaik, JaanTallinna Tehnikaülikooli aastaraamat 20072008 / lk. 275-278

Mixed hierarchical-functional fault models for targeting sequential coresRaik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi; Jenihhin, MaksimJournal of systems architecture2008 / 3/4, p. 465-477 : ill

Mixed-level defect simulation in data-paths of digital systemsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, Marina23rd International Conference on Microelectronics : MIEL 2002, Niš, Yugoslavia, 12-15 May 2002 : proceedings. Volume 22002 / p. 617-620 : ill

Mixed-level deterministic-random test generation for digital systemsJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 19981998 / p. 335-340

Mixed-level identification of fault redundancy in microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Gürsoy, Cemil Cem; Raik, JaanLATS 2019 : 20th IEEE Latin American Test Symposium : Santiago, Chile,
March 11th - 13th 20192019 / 6 p. : ill https://doi.org/10.1109/LATW.2019.8704591

Mixed-level test generator for digital systemsBrik, Marina; Jervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering1997 / 4, p. 271-282 : ill

Modeling and experimental analysis of the mass loading effect on micro-ionic polymer actuators using step response identificationDadras, Iman; Ghenna, Sofiane; Grondel, Sébastien; Cattan, Éric; Raik, Jaan; Aabloo, Alvo; Banerji, SaoniJournal of Microelectromechanical Systems2021 / p. 243–252 : ill https://doi.org/10.1109/JMEMS.2021.3060897 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Modeling and simulation of circuits with shared structurally synthesized BDDsUbar, Raimund-Johannes; Jürimägi, Lembit; Raik, Jaan; Viies, VladimirMicroprocessors and microsystems2017 / p. 56-61 : ill http://dx.doi.org/10.1016/j.micpro.2016.09.006

Modeling for multi-view interference analysis of design aspects in MPSoC designsVain, Jüri; Apneet Kaur; Tsiopoulos, Leonidas; Raik, Jaan; Jenihhin, MaksimRESCUE 2017 : Workshop on Reliability, Security and Quality : ETS17 Fringe Workshop, May 25-26, 2017, Limassol, Cyprus2017 / p. 1-6 http://www.ets17.org.cy/workshop/rescue-workshop.html

Modeling microprocessor faults on high-level decision diagrams [Electronic resource]Ubar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, Maksim; Istenberg, Martin; Wuttke, Heinz-DietrichDSN 2008 : supplemental : 2008 IEEE International Conference on Dependable Systems & Networks With FTCS & DCC (DSN) : June 24-27, 2008, Anchorage, Alaska2008 / p. C17-C22 : ill. [CD-ROM]

Module level defect simulation in digital circuitsKuzmicz, Wieslaw; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering2001 / 4, p. 253-268

Multi-fragment Markov model guided online test generation for MPSoCVain, Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Apneet Kaur; Jenihhin, Maksim; Raik, JaanICTERI 2017 : ICT in Education, Research and Industrial Applications. Integration, Harmonization and Knowledge Transfer : proceedings of the 13th International Conference on ICT in Education, Research and Industrial Applications. Integration, Harmonization and Knowledge Transfer, Kyiv, Ukraine, May 15-18, 20172017 / p. 594-607 : ill http://www.scopus.com/inward/record.uri?eid=2-s2.0-85020540459&partnerID=40&md5=af226e25c344c52689f23bf5c39cc267 http://ceur-ws.org/Vol-1844/10000594.pdf

Multi-level fault simulation of digital systems on decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaThe First IEEE International Workshop on Electronic Design, Test and Applications : DELTA 2002, 29-31 January 2002, Christchurch, New Zealand : proceedings2002 / p. 86-91 : ill

Multiple fault diagnosis with BDD based Boolean differential equationsUbar, Raimund-Johannes; Raik, Jaan; Kostin, Sergei; Kõusaar, JaakBEC 2012 : 2012 13th Biennial Baltic Electronics Conference : proceedings of the 13th Biennial Baltic Electronics Conference : October 3-5, 2012, Tallinn, Estonia2012 / p. 77-80 : ill

Multiple stuck-at-fault detection theoremUbar, Raimund-Johannes; Kostin, Sergei; Raik, JaanProceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 18-20, 2012 Tallinn, Estonia2012 / p. 236-241 : ill

Multiple-objective backtrace for solving test generation constraintsMekler, A.; Raik, JaanInternational Symposium on System-on-Chip : November 19-21, 2003, Tampere, Finland : proceedings2003 / p. 123-126 : ill

Multi-valued simulation with binary decision diagramsUbar, Raimund-Johannes; Raik, JaanProceedings IEEE European Test Workshop, Cagliari, Italy, May 28-30, 19971997 / p. 28-29

Multi-view modeling for MPSoC design aspects [Online resource]Vain, Jüri; Apneet Kaur; Tsiopoulos, Leonidas; Raik, Jaan; Jenihhin, MaksimBEC 2018 : 2018 16th Biennial Baltic Electronics Conference (BEC) : proceedings of the 16th Biennial Baltic Electronics Conference, October 8-10, 20182018 / 4 p.: ill https://doi.org/10.1109/BEC.2018.8600986

Mutation analysis for systemC designs at TLMGuarnieri, Valerio; Bombieri, Nicola; Pravadelli, Graziano; Fummi, Franco; Hantson, Hanno; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes12th IEEE Latin American Test Workshop (LATW) : Porto de Galinhas, Brasil, 27-30 March 20112011 / [6] p

Mutation analysis with high-level decision diagramsHantson, Hanno; Raik, Jaan; Jenihhin, Maksim; Tšepurov, Anton; Ubar, Raimund-Johannes; Guglielmo, Giuseppe di; Fummi, FrancoLATW2010 : 11th Latin-American TestWorkshop, March 28-31, 2010, Punta del Este, Uruguay2010 / [6] p. [CD-ROM]

Mutation-based verification and error correction in high-level designs = Mutatsioonidel põhinev verifitseerimine ja vigade parandamine kõrgtaseme skeemidesHantson, Hanno2015

Nanoelectronics aging mitigation using SSBDD based techniques and dedicated sensorsUbar, Raimund-Johannes; Vargas, Fabian; Jenihhin, Maksim; Raik, JaanMEDIAN Workshop on Circuit Reliability : Modeling and Monitoring, Rome, Italy, February 25, 20132013 / [1] p

Negative correlation between functional connectivity and small-worldness in the alpha frequency band of a healthy brainPäeske, Laura; Hinrikus, Hiie; Lass, Jaanus; Raik, Jaan; Bachmann, MaieFrontiers in Physiology2020 / Art. nr. 910 https://doi.org/10.3389/fphys.2020.00910 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

New built-in self-test scheme for SoC interconnectJutman, Artur; Ubar, Raimund-Johannes; Raik, JaanThe 9th World Multi-Conference on Systemics, Cybernetics and Informatics : WMSCI 2005 : July 10-13, 2005, Orlando, Florida, USA. Vol. IV2005 / p. 19-24 : ill

New categories of Safe Faults in a processor-based Embedded SystemGürsoy, Cemil Cem; Jenihhin, Maksim; Oyeniran, Adeboye Stephen; Piumatti, Davide; Raik, Jaan; Sonza Reorda, Matteo; Ubar, Raimund-Johannes2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Cluj-Napoca, Romania : proceedings2019 / 4 p. : ill https://doi.org/10.1109/DDECS.2019.8724642

New fault models and self-test generation for microprocessors using High-Level Decision DiagramsJasnetski, Artjom; Raik, Jaan; Tšertov, Anton; Ubar, Raimund-Johannes2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings2015 / p. 251-254 : ill

New method of testability calculation to guide RT-level test generationRaik, Jaan; Nõmmeots, Tanel; Ubar, Raimund-Johannes4th IEEE Latin-American Test Workshop : LATW2003 : Natal, Brazil, February 16-19, 20032003 / p. 46-51 : ill

New technique for hierarchical identification of untestable faults in sequential circuitsKrivenko, Anna; Ubar, Raimund-Johannes; Raik, Jaan; Kruus, MargusInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / lk. 155-158 : ill

Noore teadlase preemia on ihaldusväärne : [Vabariigi Presidendi kultuurirahastu noore teadlase preemia sai Jaan Raik : Jaan Raigi kommentaaridega]Lill, Anne; Raik, JaanLinnaleht2004 / lk. 4 : fot

Novel architectures for contractive autoencoders with embedded learningKerner, Madis; Tammemäe, Kalle; Raik, Jaan; Hollstein, Thomas2020 17th Biennial Baltic electronics conference, Tallinn, Estonia, October 6-8, 2020 : proceedings2020 / 6 p. : ill https://doi.org/10.1109/BEC49624.2020.9277246

Novel Neural Network accelerator architectures for FPGAs = Uudsed närvivõrkude kiirendite arhitektuurid FPGAdeleKerner, Madis2024 https://www.ester.ee/record=b5675484*est https://digikogu.taltech.ee/et/Item/3568fe35-19c3-43e6-9525-73c79371ab13 https://doi.org/10.23658/taltech.16/2024

A novel random approach to diagnostic test generationOsimiry, Emmanuel Ovie; Ubar, Raimund-Johannes; Kostin, Sergei; Raik, Jaan2nd IEEE NORCAS Conference : 1-2 November 2016, Copenhagen, Denmark2016 / [4] p. : ill https://doi.org/10.1109/NORCHIP.2016.7792915

NV-SP: A new high performance and low energy NVM-Based scratch padShalabi, Ameer; Paul, Kolin; Ghasempouri, Tara; Raik, Jaan2020 IEEE Computer Society Annual Symposiumon VLSI : ISVLSI 2020, 6–8 July 2020, Limassol, Cyprus2020 / art. 19876866, p. 54−59 https://doi.org/10.1109/ISVLSI49217.2020.00020

Nädala lood: jätkuvad halvad uudised ehitusestRõuk, Viivikaaripaev.ee2023 Nädala lood: jätkuvad halvad uudised ehitusest

On efficient logic-level simulation of digital circuits represented by the SSBDD modelJutman, Artur; Raik, Jaan; Ubar, Raimund-Johannes23rd International Conference on Microelectronics : MIEL 2002, Niš, Yugoslavia, 12-15 May 2002 : proceedings. Volume 22002 / p. 621-624 : ill

On reusability of verification assertions for testingJenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Tšepurov, AntonBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 151-154 : ill

On reusability of verification assertions for testingJenihhin, Maksim; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / p. 43-46 : ill

On test generation for microprocessors for extended class of functional faultsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC: New technology enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 : Revised and Extended Selected Papers2020 / p. 21-44 https://doi.org/10.1007/978-3-030-53273-4 Conference proceedings at Scopus Article at Scopus

On the combined use of HLDDs and EFSMs for functional ATPGDi Guglielmo, Giuseppe; Fummi, Franco; Jenihhin, Maksim; Pravadelli, Graziano; Raik, Jaan; Ubar, Raimund-Johannes5th IEEE East-West Design & Test Symposium EWDTS 2007 : September 7-10, 2007, Yerevan, Armenia2007 / p. 503-508 : ill

On the reuse of TLM mutation analysis at RTLGuarnieri, Valerio; Hantson, Hanno; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications2012 / p. 435-448 : ill

On using genetic algorithm for test generationBrik, Marina; Raik, Jaan; Ubar, Raimund-Johannes; Ivask, EeroBEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia2004 / p. 233-236 : ill

Open-source framework and practical considerations for translating RTL VHDL to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, JaanIP-SoC 2012 : IP Embedded System Conference & Exhibition : Grenoble, France, Dec. 4-5, 20122012

Optimization methodologies for Cycle-Accurate SystemC models converted from RTL VHDLSaif Abrar, Syed; Jenihhin, Maksim; Raik, JaanIP-SoC 2013 : IP embbeded system conference and exhibition : Grenoble, France, November 6-7, 20132013

Optimization of structurally synthesized BDDsUbar, Raimund-Johannes; Vassiljeva, T.; Raik, Jaan; Jutman, Artur; Tombak, Mati; Peder, AhtiProceedings of the Fourth IASTED International Conference on Modelling, Simulation, and Optimization : August 17-19, 2004, Kavai, Hawaii, USA2004 / p. 234-240 : ill

Parallel critical path tracing fault simulation in sequential circuitsKõusaar, Jaak; Ubar, Raimund-Johannes; Kostin, Sergei; Devadze, Sergei; Raik, JaanProceedings of 25th International Conference MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS : MIXDES 2018 : Gdynia, Poland, June 21–23, 20182018 / p. 305-310 : ill https://doi.org/10.23919/MIXDES.2018.8436880

Parallel exact critical path tracing fault simulation with reduced memory requirementsDevadze, Sergei; Ubar, Raimund-Johannes; Raik, Jaan; Jutman, Artur4th International Conference on Design and Technology of Integrated Systems in Nanoscal Era : DTIS'09 : Cairo, Egypt, April 6-9, 20092009 / p. 155-160 : ill https://ieeexplore.ieee.org/document/4938046

Parallel fault backtracing for calculation of fault coverageUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, ArturProceedings of the ASP-DAC 2008 : [13th] Asia and South Pacific Design Automation Conference 2008 : January 21-24, 2008, COEX, Seoul, Korea2008 / p. 667-672 : ill

Parallel fault backtracing for calculation of fault coverageUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, Artur43rd International Conference on Microelectronics, Devices and Materials and the Workshop on Electronic Testing : September 12. - September 14.2007, Bled, Slovenia : MIDEM conference 2007 proceedings2007 / p. 165-170 : ill

Parallel fault simulation in digital circuitsAarna, Margit; Raik, Jaan; Ubar, Raimund-JohannesProc. of 42nd International Scientific Conference of Riga Technical University2001 / p. 91-94

Parallel fault simulation in digital circuitsAarna, Margit; Raik, Jaan; Ubar, Raimund-JohannesScientific proceedings of Riga Technical University. 7. serija, Telecommunications and electronics2001 / p. 91-94 : ill

Parallel X-fault simulation with critical path tracing technique [Electronic resource]Ubar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, ArturDATE 10 : Design, Automation & Test in Europe : Dresden, Germany, 8-12 March, 20102010 / p. 879-884 [CD-ROM]

PASCAL : timing SCA resistant design and verification flowLai, Xinhui; Jenihhin, Maksim; Raik, Jaan; Paul, Kolin2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019) : 1-3 July 2019, Greece2019 / p. 239-242 : ill https://doi.org/10.1109/IOLTS.2019.8854458

Performance analysis of cosimulating processor core in VHDL and SystemCSaif Abrar, Syed; Shyam Kiran A.; Jenihhin, Maksim; Raik, Jaan; Babu, C.Proceedings of the 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI) : 22–25 August 2013, Mysore, India2013 / p. 563-568 : ill

Pooljuhtide tehnoloogia teeviit aastaks 2016 : kiipide tehnoloogia, projekteerimise ja testi tulevikuvisioonRaik, JaanA & A2003 / 6, lk. 9-16

PrefaceUbar, Raimund-Johannes; Raik, Jaan; Vierhaus, Heinrich TheodorDesign and test technology for dependable systems-on-chip2011 / p. xxii-xxviii

Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvementBlyzniuk, M.; Kazymyra, I.; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesMicroelectronics reliability2001 / p. 2023-2040 : ill

Probabilistic equivalence checking based on high-level decision diagramsKarputkin, Anton; Ubar, Raimund-Johannes; Tombak, Mati; Raik, JaanProceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 13-15, 2011, Gottbus, Germany2011 / p. 423-428 : ill

Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 13-15, 2011, Gottbus, Germany2011 https://www.computer.org/csdl/proceedings/ddecs/2011/12OmNvTBBbs

Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 18-20, 2012 Tallinn, Estonia2012 http://www.ester.ee/record=b2777270*est

PSL assertion checkers synthesis with ASM based HLS tool ABELITEJenihhin, Maksim; Baranov, Samary; Raik, Jaan; Tihhomirov, ValentinLATW 2012 : 13th IEEE Latin-American Test Workshop proceedings : April 10th-13th, 2012, Quito, Ecuador2012 / [6 p.] : ill https://ieeexplore.ieee.org/document/6261251

PSL assertion checking using temporally extended high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications2009 / 6, p. 289-300 : ill https://pld.ttu.ee/home/maksim/phd_papers/%5B11%5D%20latw%2708.pdf

PSL assertion checking with temporally extended high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesProceedings of the 9th IEEE Latin-American Test Workshop : LATW2008 : February 17-20, 2008, Puebla, Mexico2008 / p. 49-54 : ill

QoSinNoC: analysis of QoS-aware NoC architectures for mixed-criticality applicationsAvramenko, Serhiy; Azad, Siavoosh Payandeh; Niazmand, Behrad; Raik, Jaan; Jenihhin, Maksim21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems : DDECS 2018 : Budapest, Hungary 25-27 April, 2018 : proceedings2018 / p. 67-72 : ill https://doi.org/10.1109/DDECS.2018.00-10

Rahvusvaheline süsteem-kiibil teaduskonverents Soomes - Tampere SoC Symposium 2003Raik, JaanA & A2003 / 6, lk. 56

Ransomware attack as Hardware Trojan : a feasibility and demonstration studyAlmeida, Felipe; Imran, Malik; Raik, Jaan; Pagliarini, Samuel NascimentoIEEE Access2022 / p. 44827-44839 https://doi.org/10.1109/ACCESS.2022.3168991 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Register-transfer level deductive fault simulation using decision diagramsReinsalu, Uljana; Raik, Jaan; Ubar, Raimund-JohannesBEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia2010 / p. 193-196 : ill

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPGPalermo, N.; Tihhomirov, Valentin; Copetti, Thiago; Jenihhin, Maksim; Raik, Jaan; Kostin, Sergei2015 16th Latin American Test Symposium (LATS 2015) : Puerto Vallarta, Mexico, 25-27 March 20152015 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2015.7102405

Rejuvenation of NBTI-impacted processors using evolutionary generation of assembler programsPellerey, Francesco; Jenihhin, Maksim; Squillero, Giovanni; Raik, Jaan; Sonza Reorda, Matteo; Tihhomirov, Valentin; Ubar, Raimund-Johannes2016 IEEE 25th Asian Test Symposium : 21-24 November 2016, Hiroshima, Japan2016 / p. 304-309 : ill https://doi.org/10.1109/ATS.2016.57

Reliability improvements for multiprocessor systems by health-aware task schedulingSchmidt, Robert; Massoud, Rehab; Raik, Jaan; Garcia-Ortiz, Alberto; Drechsler, Rolf2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS 2018) : 2 - 4 July 2018, Spain2018 / p. 247-250 : ill http://dx.doi.org/10.1109/IOLTS.2018.8474101

A rescue demonstrator for interdependent aspects of reliability, security and quality towards a complete EDA flowRaik, Jaan; Jenihhin, MaksimProceedings of the 2020 Design, Automation & Test in Europe Conference &Exhibition (DATE 2020), 9 to 13 March, 2020, Grenoble, France2020 / p. 58 https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9116424

RESCUE EDA Toolset for interdependent aspects of reliability, security and quality in nanoelectronic systems designGürsoy, Cemil Cem; Cardoso Medeiros, Guilherme; Chen, Juanho; Balakrishnan, Aneesh; Lai, Xinhui; Bagbaba, Ahmet Cagri; Raik, Jaan; Jenihhin, MaksimDATE 20192019 / 1 p. : ill https://doi.org/10.5281/zenodo.3362529 https://past.date-conference.com/

RESCUE: interdependent challenges of reliability, security and quality in nanoelectronic systemsJenihhin, Maksim; Raik, Jaan2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 9-13 March 2020, Grenoble, France : proceedings2020 / art. 19690741 , 6 p https://doi.org/10.23919/DATE48585.2020.9116558

Research environment for teaching digital testIvask, Eero; Jutman, Artur; Orasson, Elmet; Raik, Jaan; Ubar, Raimund-Johannes; Wuttke, Heinz-DietrichSynergies between Information and Automation : 49. Internationales Wissenschaftliches Kolloquium, 27.-30.9.2004, Technische Universität Ilmenau, Germany. Volume 22004 / p. 468-473 : ill

Research in digital design and test at Tallinn University of TechnologyUbar, Raimund-Johannes; Jervan, Gert; Jutman, Artur; Raik, Jaan; Ellervee, Peeter; Kruus, MargusRadioelectronics & informatics2008 / p. 4-12 : ill http://www.ewdtest.com/ri/%E2%84%96-1-40-january-march-2008/

Research on digital system design and test at Tallinn University of TechnologyUbar, Raimund-Johannes; Ellervee, Peeter; Hollstein, Thomas; Jervan, Gert; Jutman, Artur; Kruus, Margus; Raik, JaanResearch in Estonia : present and future2011 / p. 184-205 : ill

Reseeding using compaction of pre-generated LFSR sequencesJutman, Artur; Aleksejev, Igor; Raik, Jaan; Ubar, Raimund-JohannesICECS 2008 : The 15th IEEE International Conference on Electronics, Circuits and Systems : 31st August to 3rd September 2008, Malta : conference guide2008 / p. 215

Reseeding using compaction of pre-generated LFSR sub-sequencesJutman, Artur; Aleksejev, Igor; Raik, Jaan; Ubar, Raimund-JohannesICECS 2008 : The 15th IEEE International Conference on Electronics, Circuits and Systems : Malta2008 / p. 1290-1295 : ill http://dx.doi.org/10.1109/ICECS.2008.4675096

Resting EEG functional connectivity and graph theoretical measures for discrimination of depressionOrgo, Laura; Bachmann, Maie; Kalev, Kaia; Järvelaid, Mari; Raik, Jaan; Hinrikus, Hiie4th IEEE EMBS International Conference on Biomedical and Health Informatics, BHI 2017 : Orlando, Florida, USA, 16-19 February 20172017 / p. 389-392 : ill https://doi.org/10.1109/BHI.2017.7897287

RTL assertion mining with automated RTL-to-TLM abstractionGhasempouri, Tara; Danese, Alessandro; Pravadelli, Graziano; Bombieri, Nicola; Raik, JaanProceedings of the 2019 Forum on specification & Design Languages (FDL)2019 / 8 p. : ill https://doi.org/10.1109/FDL.2019.8876941

RT-level identification of potentially testable initialization faultsRaik, Jaan; Fujiwara, Hideo; Krivenko, AnnaThe Ninth IEEE Workshop on RTL and High Level Testing (WRTLT 2008), Sapporo, Japan2008 / [6] p

RT-level test point insertion for sequential circuitsRaik, Jaan; Govind, Vineeth; Ubar, Raimund-JohannesIWoTA 2004 : IEEE 1st International Workshop on Testability Assessment : November 2, 2004, Rennes, France : proceedings2004 / p. 34-40 : ill

Ränioruga sideme katkestamine ohustab meie IT-sektoritRaik, Jaanpostimees.ee2023 / Lk. 13 Ränioruga sideme katkestamine ohustab meie IT-sektorit

SCAAT: Secure cache alternative address table for mitigating cache logical side-channel attacksShalabi, Ameer; Ghasempouri, Tara; Ellervee, Peeter; Raik, Jaan2020 23rd Euromicro Conference on Digital System Design (DSD), 26-28 August 2020, Kranj, Slovenia2020 / art, 20035366, p. 213−217 https://doi.org/10.1109/DSD51259.2020.00043

Scalable algorithm for structural fault collapsing in digital circuitsUbar, Raimund-Johannes; Jürimägi, Lembit; Orasson, Elmet; Raik, Jaan2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) : October 5-7, 2015, Daejeon, Korea2015 / p. 171-176 : ill

A security verification template to assess cache architecture vulnerabilitiesGhasempouri, Tara; Raik, Jaan; Paul, Kolin; Reinbrecht, Cezar; Hamdioui, Said; Taouil, M.2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), April 22nd – 24th 2020 Novi Sad, Serbia : Proceedings2020 / art. 9095707, 6 p https://doi.org/10.1109/DDECS50862.2020.9095707

Sequential circuit test generation using decision diagram modelsRaik, Jaan; Ubar, Raimund-JohannesDesign, Automation and Test in Europe : DATE : Conference and Exhibition 1999 : Munich, Germany, March 9-12, 1999 : proceedings1999 / p. 736-740: ill

Sequential circuits BIST synthesis from signal specificationsRaik, Jaan; Jenihhin, Maksim; Adelbert, RainProceedings 23rd NORCHIP Conference : Oulu, Finland, 21-22 November 20052005 / p. 196-199 : ill

Sequential circuits BIST with status bit controlRaik, Jaan; Orasson, Elmet; Ubar, Raimund-JohannesProceedings of the 11th International Conference : Mixed Design of Integrated Circuits and Systems : MIXDES 2004 : Szczecin, Poland, 24-26 June 20042004 / p. 507-510 : ill

Sequential test set compaction in LFSR reseedingJutman, Artur; Aleksejev, Igor; Raik, JaanDesign and test technology for dependable systems-on-chip2011 / p. 476-493 : ill

A set of tools for estimating quality of built-in self-test in digital circuitsJervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the International Symposium on Signals, Circuits and Systems, Iasi (Romania), October 2-3, 19971997 / p. 362-365

Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuitsUbar, Raimund-Johannes; Jürimägi, Lembit; Raik, Jaan2015 Nordic Circuits and Systems Conference (NORCAS) : NORCHIP & International Symposium on System-on-Chip (SoC) : 1st IEEE NORCAS Conference : 26-28 October 2015, Oslo, Norway2015 / [4] p. : ill http://dx.doi.org/10.1109/NORCHIP.2015.7364406

Side-channel attacks on triple modular redundancy schemesAlmeida, Felipe; Aksoy, Levent; Raik, Jaan; Pagliarini, Samuel Nascimento2021 IEEE 30th Asian Test Symposium ATS 2021 : proceedings2021 / p. 79-84 : ill https://doi.org/10.1109/ATS52891.2021.00026 Conference Proceedings at Scopus Article at Scopus Article at WOS

Simulation of digital systems with high-level decision diagramsMorawiec, Adam; Raik, Jaan; Ubar, Raimund-JohannesThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 35-38 : ill

Simulation-based hardware verification with high-level decision diagrams = Simuleerimisel põhinev riistvara verifitseerimine kõrgtaseme otsustusdiagrammidelJenihhin, Maksim2008 https://www.ester.ee/record=b2431332*est

Simulation-based verification with APRICOT framework using high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesEast-West Design & Test Symposium : Moscow, September 18-21, 20092009 / p. 13-16 : ill

SoC and NoC test technology [Electronic resource] : [PowerPoint presentation]Raik, JaanDesign and Test Technology for Dependable Hardware/Software Systems : DEDIS/DAAD Summer Academy : BTU Cottbus, Sept. 1st-12th, 20082008 / [41] p. : ill. [CD-ROM]

SoCDep2 : a framework for dependable task deployment on many-core systems under mixed-criticality constraintsAzad, Siavoosh Payandeh; Niazmand, Behrad; Ellervee, Peeter; Raik, Jaan; Jervan, Gert; Hollstein, Thomas2016 11th International Symposium on Reconfigurable Communication‐centric Systems‐on‐Chip (ReCoSoC) : June 27‐29, 2016, Tallinn, Estonia2016 / [6] p. : ill https://doi.org/10.1109/ReCoSoC.2016.7533903

Software-based mitigation for memory address decoder agingKraak, D. H. P.; Gürsoy, Cemil Cem; Jenihhin, Maksim; Raik, JaanLATS 2019 : 20th IEEE Latin American Test Symposium : Santiago, Chile, March 11th - 13th 20192019 / 6 p. : ill https://doi.org/10.1109/LATW.2019.8704595

Software-level TMR approach for on-board data processing in space applicationsJanson, Karl; Treudler, Carl Johann; Hollstein, Thomas; Raik, Jaan; Jenihhin, Maksim; Fey, Goerschwin21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems : DDECS 2018 : Budapest, Hungary 25-27 April, 2018 : proceedings2018 / p. 147-152 : ill https://doi.org/10.1109/DDECS.2018.00033

SPICE-inspired fast gate-level computation of NBTI-induced delays in nanoscale logicKostin, Sergei; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, Maksim2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings2015 / p. 223-228 : ill

SSBDD model : advantageous properties and efficient simulation algorithmsRaik, Jaan; Jutman, Artur; Ubar, Raimund-JohannesETW'02 : 7th IEEE European Test Workshop, Gorfu Greece, May 26-29, 2002 : informal digest2002 / p. 345-346 : ill

SSBDDs : advantageous model and efficient algorithms for digital circuit modeling, simulation & testJutman, Artur; Raik, Jaan; Ubar, Raimund-Johannes5th International Workshop on Boolean Problems : September 19-20, 2002,
Freiberg (Sachsen) : proceedings2002 / p. 157-166 : ill

SSBDDs and double topology for multiple fault reasoningUbar, Raimund-Johannes; Kostin, Sergei; Raik, JaanProceedings of IEEE East-West Design & Test Symposium (EWDTS’2012) : Kharkov, Ukraine, September 14–17, 20122012 / p. 23-28

Structural fault collapsing by superposition of BDDs for test generation in digital circuitsUbar, Raimund-Johannes; Mironov, Dmitri; Raik, Jaan; Jutman, ArturProceedings of the Eleventh International Symposium on Quality Electronic Design ISQED 2010 : March 22-24, 2010 San Jose, California USA2010 / p. 250-257 : ill

Structurally synthesized binary decision diagramsJutman, Artur; Peder, Ahti; Raik, Jaan; Tombak, Mati; Ubar, Raimund-JohannesBoolean Problems : 6th International Workshop : September 23-24, 2004, Freiberg2004 / p. 271-278 : ill

Structurally synthesized multiple input BDDs for simulation of digital circuitsUbar, Raimund-Johannes; Mironov, Dmitri; Raik, Jaan; Jutman, Artur16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009 : Yasmine Hammamet, Tunesia, 13-19 December, 20092009 / p. 451-454 : ill http://dx.doi.org/10.1109/ICECS.2009.5410895

Structurally synthesized multiple input BDDs for speeding up logic-level simulation of digital circuitsMironov, Dmitri; Ubar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, Artur13th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : DSD 2010 : Lille, France, 1-3 September 2010 : proceedings2010 / p. 658-663 : ill

Surrogate data method requires end-matched segmentation of electroencephalographic signals to estimate non-linearityPäeske, Laura; Bachmann, Maie; Põld, Toomas; Oliveira, Sara Pereira Mendes de; Lass, Jaanus; Raik, Jaan; Hinrikus, HiieFrontiers in physiology2018 / 1350 ; 9 p. : ill https://doi.org/10.3389/FPHYS.2018.01350 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Süvatehnoloogiate alternatiivsed arengutrajektoorid ja nende tähendus Eestile : lõpparuanneKoppel, Kaupo; Kuusik, Alar; Arrak, Kadri; Raik, Jaan; Niidu, Allan; Kõks, Kerttu-Liis; Lahtvee, Petri-Jaan2023 https://media.voog.com/0000/0037/5345/files

Synthesis of high-level decision diagrams for functional test pattern generationUbar, Raimund-Johannes; Raik, Jaan; Karputkin, Anton; Tombak, MatiProceedings of the 16th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2009 : Lodz, Poland, 25-27 June, 20092009 / p. 519-524 : ill

Synthesis of multiple fault oriented test groups from single fault test sets [Electronic resource]Ubar, Raimund-Johannes; Kostin, Sergei; Raik, Jaan2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) : 26-28 March 2013, Abu Dhabi, UAE2013 / p. 36-41 : ill [CD-ROM]

Systematic review of fault tolerant techniques in underwater sensor networksVihman, Lauri; Kruusmaa, Maarja; Raik, JaanSensors2021 / art. 3264 https://doi.org/10.3390/s21093264 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

SystemC-based loose models : RTL abstraction for design understandingAbrar, Syed Saif; Jenihhin, Maksim; Raik, JaanWorkshop on Design Automation for Understanding Hardware Designs DUHDe 2015 : Grenoble, March 13, 20152015 / p. 1-6

SystemC-based loose models for simulation speed-up by abstraction of RTL IP coresAbrar, Syed Saif; Jenihhin, Maksim; Raik, Jaan2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings2015 / p. 71-74 : ill http://dx.doi.org/10.1109/DDECS.2015.39

zamiaCAD : open source platform for advanced hardware designTšepurov, Anton; Jenihhin, Maksim; Raik, JaanDATE 2011 University Booth : Design Automation and Test in Europe : Grenoble, France, March 14-18, 20112011 / [2] p.: ill

zamiaCAD : understand, develop and debug hardware designsJenihhin, Maksim; Tihhomirov, Valentin; Saif Abrar, Syed; Raik, Jaan; Bartsch, GünterDUHDe : 1st Workshop on Design Automation for Understanding Hardware Designs : March 28, 2014 : Friday Workshop at DATE 2014, Dresden, Germany2014 / p. 1-6

Targeting conditional operations in sequential test pattern generationRaik, Jaan; Ubar, Raimund-Johannes9th European Test Symposium : ETS'04 : Congress Center, Ajaccio, Corsica, France,
May 23-26, 20042004 / p. 17-18 : ill

Teaching advanced test issues in digital electronicsUbar, Raimund-Johannes; Orasson, Elmet; Raik, Jaan; Wuttke, Heinz-DietrichProceedings of the 6th IEEE International Conference on Information Technology Based Higher Education and Training : ITHET : July 7-9, 2005, Juan Dolio, Dominican Republic2005 / p. S2B-1 - S2B-6 : ill http://dx.doi.org/10.1109/ITHET.2005.1560318

Teaching diagnostic modeling of digital systems with decision diagrams [Electronic resource]Ubar, Raimund-Johannes; Raik, Jaan; Mironov, Dmitri; Evartson, Teet; Orasson, Elmet; Aarna, Margit; Wuttke, Heinz-DietrichProceedings of 12th IASTED International Conference on Computers and Advanced Technology in Education - CATE 2009 : St.Thomas, US, November 22-24, 20092009 / p. 1-6. [CD-ROM]

Teaching research in the laboratory using diagnosis environment for digital systemsKostin, Sergei; Ubar, Raimund-Johannes; Raik, Jaan; Aarna, Margit; Brik, Marina; Wuttke, Heinz-Dietrich2009 EAEEIE annual conference : 20th Annual Conference of the European Association for Education in Electrical and Information Engineering : Valencia, Spain, June 22-24, 20092009 / p. 280-283 https://ieeexplore.ieee.org/document/5335462

Teaching test and design for testability with TURBO-TESTER softwareJervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 3rd Workshop on Mixed Design of Integrated Circuits and Systems, Lodz, May 19961996 / p. 589-594

Teadlase aju otsib vigu unes : [intervjuu Jaan Raigiga]Raik, Jaan; Ideon, ArgoEesti Ekspress2004 / 16. dets., lk. A18-A19 : fot https://ekspress.delfi.ee/artikkel/69048013/teadlase-aju-otsib-vigu-oosel-unes

Teaduskonverentsi korraldamine Eestis nõuab paar aastat eeltööd : [intervjuu Jaan Raigiga]Raik, Jaan; Kiviorg, KristoÄripäev2006 / 2. märts, Konverentsiturism, lk. 3

Techniques for automated localization and correction of design errorsRaik, JaanCREDES Summer School : Dependable Systems Design : handouts2011 / p. 107-118 : ill

Techniques for robust routing, communication and computation in multiprocessor systems = Robustse marsruutimise, side ja arvutuse tehnikad mitmeprotsessorilistes süsteemidesJanson, Karl2021 https://www.ester.ee/record=b5396084*est https://digikogu.taltech.ee/et/Item/c9091d5c-dcd8-4b21-95a7-84ead85241e6 https://doi.org/10.23658/taltech.3/2021

Tehnikaülikooli teadurid teevad mikrokiipide vallas ajalugu : [arvutitehnika instituudi vanemteadur Jaan Raik jagab selgitusi]Tooming, Urmas; Raik, JaanPostimees2009 / 28. juuli, lk. 7 : fot https://majandus.postimees.ee/146505/tehnikaulikooli-teadurid-teevad-mikrokiipide-vallas-ajalugu

Temporally extended high-level decision diagrams for PSL assertions simulationJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesProceedings : Thirteenth IEEE European Test Symposium : ETS 2008 : 25-29 May 2008, Verbania, Italy2008 / p. 61-68 : ill

10th IEEE European Test SymposiumUbar, Raimund-Johannes; Prinetto, Paolo; Raik, JaanIEEE journal of design & test of computers2005 / p. 480-481 : phot http://dx.doi.org/10.1109/MDT.2005.106

Tere, tenuur!Raik, JaanMente et Manu2017 / lk. 4-5 : fot https://www.ttu.ee/public/m/mente-et-manu/MM_05_2017/mobile/index.html

Test configurations for diagnosing faulty links in NoC switchesRaik, Jaan; Ubar, Raimund-Johannes; Govind, Vineeth12th IEEE European Test Symposium ETS 2007 : 20-24 May 2007, Freiburg, Germany : proceedings2007 / p. 29-34 : ill http://dx.doi.org/10.1109/ETS.2007.41

Test configurations for diagnosing faulty links in NoC switchesRaik, Jaan; Ubar, Raimund-Johannes; Govind, VineethInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 33-37 : ill

Test cover calculation in digital systems with word-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaВестник Томского государственного университета2002 / с. 315-319 : ил

Test development and deployment tool-set for mixed-signal and digital devicesMellik, Andres; Raik, JaanBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 163-166 : ill

Test generation with structurally synthesized BDD modelsRaik, Jaan; Ubar, Raimund-JohannesProceedings of the 5th Electronic Devices and Systems Conference, Brno, June 11-12, 19981998 / p. 66-68

Test set minimization using bipartite graphsMarkus, Antti; Raik, Jaan; Ubar, Raimund-JohannesBEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 175-178: ill

Test synthesis from register-transfer level descriptionsRaik, Jaan; Paomets, PriiduBEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 311-314: ill

Testability analysis for efficient register-transfer level test generation [Electronic resource]Nõmmeots, Tanel; Raik, Jaan; Ubar, Raimund-Johannes9th International Conference MIXDES 2002 : Mixed Design of Integrated Circuits and Systems, Wroclaw, Poland, 20-22 June 20022002 / [4] p. [CD-ROM]

Testability guided hierarchical test generation with decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Nõmmeots, Tanel20th IEEE NORCHIP Conference : Copenhagen, Denmark, November 11-12, 20022002 / p. 265-271

Testing strategies for networks on chipUbar, Raimund-Johannes; Raik, JaanNetworks on chip2003 / p. 131-152 : ill

Testing toolsRaik, JaanHandbook of testing electronic systems2005 / p. 373-378 : ill

Testing tools for training and educationBalaž, M.; Jutman, Artur; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 12th International Conference : Mixed Design of Integrated Circuits and Systems : MIXDES 2005 : Krakow, Poland, 22-25 June, 2005. Vol. 1 of 22005 / p. 671-676 : ill

Timing-critical path analysis with structurally synthesized BDDsUbar, Raimund-Johannes; Jürimägi, Lembit; Jenihhin, Maksim; Raik, Jaan; Olugbenga, Niyi-Leigh; Viies, Vladimir2018 7th Mediterranean Conference on Embedded Computing (MECO)2018 / 6 p. : ill https://doi.org/10.1109/MECO.2018.8406051

Towards formal verification of cache access-based side-channel attacksNiazmand, Behrad; Reinbrecht, Cezar; Raik, Jaan; Jervan, Gert; Sepulveda, JohannaTestmethoden und Zuverlässigkeit von Schaltungen und Systemen, TUZ 20192019 / 2 p. : tab http://www.informatik.uni-bremen.de/tuz/2019

Towards multidimensional verification : where functional meets non-functionalJenihhin, Maksim; Lai, Xinhui; Ghasempouri, Tara; Raik, Jaan2018 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC) : 30-31 October 2018, Tallinn, Estonia : proceedings in IEEE Xplore2018 / 7 p. : ill https://doi.org/10.1109/NORCHIP.2018.8573495

Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebraKõusaar, Jaak; Ubar, Raimund-Johannes; Devadze, Sergei; Raik, JaanMicroprocessors and microsystems2015 / p. 1130-1138 : ill http://dx.doi.org/10.1016/j.micpro.2015.05.003

Triple fixed-point MAC unit for deep learningKerner, Madis; Tammemäe, Kalle; Raik, Jaan; Hollstein, ThomasProceedings of the 2021 Design, Automation & Test in Europe (DATE 2021), 1-5 February 2021 : Virtual Conference2021 / p. 1404-1407 https://doi.org/10.23919/DATE51398.2021.9474020

TTBist: a DfT tool for enhancing functional test for SoCHermann, K.; Raik, Jaan; Jenihhin, MaksimBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 191-194 : ill

Turbo tester - diagnostic package for research and trainingAarna, Margit; Ivask, Eero; Jutman, Artur; Orasson, Elmet; Raik, Jaan; Ubar, Raimund-Johannes; Vislogubov, Vladislav; Wuttke, Heinz-DietrichRadioelectronics and informatics2003 / p. 69-73 : ill

Turbo tester : a CAD system for teaching digital testJervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesMicroelectronics education : proceedings of the 2nd European Workshop held in Noordwijkerhout, The Netherlands, 14-15 May 19981998 / p. 287-290: ill

Ultra fast parallel fault analysis on structurally synthesized BDDsUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, Artur12th IEEE European Test Symposium ETS 2007 : 20-24 May 2007, Freiburg, Germany : proceedings2007 / p. 131-136 : ill http://dx.doi.org/10.1109/ETS.2007.43

Ultra-low latency NoC testing via pseudo-random test pattern compactionTatenguem, Herve; Govind, Vineeth; Raik, JaanSoC 2012 : International Symposium on System-on-Chip 2012 : Tampere, Finland, October 11-12, 20122012 / 6 p. : ill https://ieeexplore.ieee.org/document/6376370

Understanding multidimensional verification : where functional meets non-functionalLai, Xinhui; Balakrishnan, Aneesh; Lange, Thomas; Jenihhin, Maksim; Ghasempouri, Tara; Raik, Jaan; Alexandrescu, DanMicroprocessors and microsystems2019 / art. 102867, 13 p. : ill https://doi.org/10.1016/j.micpro.2019.102867 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Untestable fault identification in sequential circuits using model-checkingRaik, Jaan; Fujiwara, Hideo; Ubar, Raimund-Johannes; Krivenko, Anna2002-2011 : 20th Anniversary compendium of papers from Asian Test Symposium2011 / p. 257-262 : ill https://ieeexplore.ieee.org/document/4711554

Untestable fault identification in sequential circuits using model-checkingRaik, Jaan; Fujiwara, Hideo; Ubar, Raimund-Johannes; Krivenko, AnnaProceedings of the 17th Asian Test Symposium ATS 2008 : November 24-27, 2008, Sapporo, Japan2008 / p. 21-26 : ill http://dx.doi.org/10.1109/ATS.2008.22

Upgrading QoSinNoC : efficient routing for mixed-criticality applications and power analysisAvramenko, Serhiy; Azad, Siavoosh Payandeh; Violante, Massimo; Niazmand, Behrad; Raik, Jaan; Jenihhin, MaksimProceedings of the 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) : October 8-10, 2018, Verona, Italy2018 / p. 207-212 : ill https://doi.org/10.1109/VLSI-SoC.2018.8644866

Using constraint solver in Test Pattern Generation ToolViilukas, Taavi; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / p. 14-17 : ill

Using simulation statistics for bug localization in RTL designsTihhomirov, Valentin; Jenihhin, Maksim; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK seitsmenda aastakonverentsi artiklite kogumik : 15.-16. novembril 2013, Haapsalu2013 / p. 107-110 : ill

Using test pattern generation tool decider in hardware verificationViilukas, Taavi; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 166-169 : ill

Uudne turvaline kiibitehnoloogiaRaik, JaanMente et Manu2021 / lk. 32-33 : fot Mente et Manu 2/2021

Web-based environment for digital electronics test toolsIvask, Eero; Raik, Jaan; Ubar, Raimund-Johannes; Schneider, AndreVirtual Enterprises and collaborative networks : IFIP 18th World Computer Congress [and] TC5/WG5.5 - 5th Working Conference on Virtual Enterprises : 22-27 August 2004, Toulouse, France2004 / p. 435-442 : ill

Web-based framework for distributed remote laboratory in the field of digital system testIvask, Eero; Jutman, Artur; Raik, Jaan; Ubar, Raimund-Johannes19th EAEEIE Annual Conference : June 29-July 2, 2008, Tallinn, Estonia : formal proceedings2008 / p. 182-187 : ill http://dx.doi.org/10.1109/EAEEIE.2008.4610183

Web-based framework for parallel distributed test [Electronic resource]Ivask, Eero; Raik, Jaan; Ubar, Raimund-Johannes2008 IEEE Design and Diagnostics of Electronic Circuits and Systems : Bratislava, Slovakia, April 16-18, 20082008 / p. 271-274 : ill. [CD-ROM]

Vector decision diagrams for simulation of digital systemsUbar, Raimund-Johannes; Morawiec, Adam; Raik, JaanDDECS'20002000 / p. 44-51

Verifying cache architecture vulnerabilities using a formal security verification flowGhasempouri, Tara; Raik, Jaan; Paul, Kolin; Reinbrecht, Cezar; Hamdioui, Said; Taouil, MottaqiallahMicroelectronics reliability2021 / art. 114085 https://doi.org/10.1016/j.microrel.2021.114085 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

VHDL based test generation systemJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 5th Electronic Devices and Systems Conference, Brno, June 11-12, 19981998 / p. 145-148

VHDL design debug framework based on zamiaCADTihhomirov, Valentin; Tšepurov, Anton; Saif Abrar, Syed; Jenihhin, Maksim; Raik, JaanDATE 2013 : Design Automation and Test in Europe, March 18-22, 2013, Grenoble, France2013 / [1] p. : ill

VILAB test generation tools running under the MOSCITO systemSchneider, Andre; Ivask, Eero; Raik, Jaan; Ubar, Raimund-JohannesVILAB User Forum : Györ, Hungary, 20012001 / [12] p