Altera Niose ja Xilinx MicroBlaze'i võrdlusTagel, MihkelA & A2005 / 1, lk. 20-28

Alternatiivsete graafide mudel loogikalülituste funktsioonide kirjeldamiseks ja analüüsiksAnton, E.; Ubar, Raimund-JohannesXXIX vabariiklik üliõpilaste teaduslik- tehniline konverents 30. märtsist - 1. aprillini 1977 : ettekannete teesid1977 / lk. 42-43 https://www.ester.ee/record=b2449987*est

Another side of categorical propositions : the Keynes-Johnson octagon of oppositionsMoktefi, Amirouche; Schang, FabienHistory and philosophy of logic2023 / p. 459-475 https://doi.org/10.1080/01445340.2022.2143711

Applying e-environments in teaching the basics of digital logicRobal, Tarmo; Kalja, AhtoProceedings MSE 2007 : 2007 IEEE International Conference on Microelectronic Systems Education : 3-4 June 2007, San Diego, CA2007 / p. 41-42 : ill https://ieeexplore.ieee.org/document/4231440/keywords#keywords

At-speed testing and test quality evaluation for high-performance pipelined systems Töökiirusel testimine ja testi kvaliteedi hindamine kõrgjõudlus-konveierarhitektuuriga süsteemideleGorev, Maksim2015 https://digi.lib.ttu.ee/i/?3953

Aufstellung von Testfolgen für logische SchaltungenPlakk, Mari; Ubar, Raimund-JohannesInternationales wissenschaftliches Kolloquium1979 / S. 93-96 https://www.ester.ee/record=b2936968*est

Boole'i algebra kasutamine automaatikalülituste projekteerimisel : loengukonspektAgur, Ustus1972 https://www.ester.ee/record=b1327567*est

Clock manipulation for heterogeneous emulation environmentEllervee, Peeter; Arhipov, Anton; Tammemäe, KalleProceedings [of] 24th IEEE Norchip Conference : Linköping, Sweden, 20-21 November 20062006 / p. 213-216 : ill https://ieeexplore.ieee.org/abstract/document/4126984

Computational kernel extraction for synthesis of power-managed sequential componentsSudnitsõn, AleksanderProceedings of the 9th IEEE International Conference on Electronics, Circuits and Systems : ICECS'2002, Dubrovnik, Croatia2002 / p. 749-752 https://ieeexplore.ieee.org/abstract/document/1046277

Design of FPGA-based circuits using hierarchical finite state machinesSkliarova, Iouliia; Sklyarov, Valery; Sudnitsõn, Aleksander2012 http://www.ester.ee/record=b2857138*est

Design of logical control devicesZakrevskij, Arkadij; Pottosin, Yu.; Cheremisinova, L.2009 https://www.ester.ee/record=b2548174*est

Digitaalarvutite operatsioonelemendid ja aritmeetikaseadmed : õppevahendMägi, Harri1978 https://www.ester.ee/record=b1274927*est

Digitaalarvutite operatsioonseadmed : õppevahendUbar, Raimund-Johannes1978 https://www.ester.ee/record=b1313974*est

Distantskaitse loogikaosaAllika, M.; Simpson, V.XXIX vabariiklik üliõpilaste teaduslik- tehniline konverents 30. märtsist - 1. aprillini 1977 : ettekannete teesid1977 / lk. 69 https://www.ester.ee/record=b2449987*est

E-learning of digital logicRobal, Tarmo; Brik, Marina; Aarna, MargitEWME 2006 proceedings : 6th International Workshop on Microelectronics Education : 8-9 June, 2006, Stockholm, Sweden2006 / p. 120-123 : ill

FPGA implementation of the polynomial curve fittingGorev, Maksim; Pesonen, VadimInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK viienda aastakonverentsi artiklite kogumik : 25.-26. novembril 2011, Nelijärve2011 / p. 121-124 : ill

FPGA-based implementation of EEG analyzerGorev, Maksim; Pesonen, Vadim; Mihhailov, Dmitri; Jenihhin, Maksim; Ellervee, PeeterDATE'11 Friday Workshop on "Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing" : Grenoble, France, March 20112011 / [1] p

FPGA-based systems in information and communicationSklyarov, Valery; Skliarova, Iouliia; Sudnitsõn, AleksanderAICT2011 : 5th International Conference on Application of Information and Communication Technologies : 12-14 October, Baku, Azerbaijan : conference proceedings2011 / p. 551-555

Hardware implementation of recursive sorting algorithms using tree-like structures and HFSM models = Rekursiivsete sortimisalgoritmide riistvaraline realiseerimine kasutades puulaadseid struktuure ja HFSM mudeleidMihhailov, Dmitri2011 https://www.ester.ee/record=b2748823*est

Identification and rejuvenation of NBTI-critical logic paths in nanoscale circuitsJenihhin, Maksim; Squillero, Giovanni; Tihhomirov, Valentin; Kostin, Sergei; Raik, Jaan; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications (JETTA)2016 / p. 273-289 : ill http://dx.doi.org/10.1007/s10836-016-5589-x

Identification and rejuvenation of NBTI-critical paths in nanoscale logic circuitsJenihhin, Maksim1st International Workshop on Reliability and Aging in Forthcoming Electronic Systems : May 28-29, 2015, Cluj-Napoca, Romania2015 / [1] p

Impulss-seadmed : laboratoorne töö nr. 5 : trigerid loogikaelementidel1986 https://www.ester.ee/record=b1240931*est

Impulss-seadmed : laboratoorne töö nr. 8 : lineaarpinge generaator1986 https://www.ester.ee/record=b2618544*est

Integraalsed loogikalülitused : katsestendi kirjeldus ja laboratoorsete tööde juhendid eriala "Elektriajamid ja tööstusseadmete automatiseerimine" 0628 üliõpilastele1989 https://www.ester.ee/record=b1216651*est

Logic and system design of digital systemsBaranov, Samary; Keevallik, Andres2008 https://www.ester.ee/record=b2358322*est

Loogikalülituste koostamise metoodika : õppevahendAriste, Andri1978 https://www.ester.ee/record=b1305228*est

Loogikaskeemid ja binaardiagrammidBuldas, AhtoAastaraamat 1994 - 1996 / Eesti Matemaatika Selts1999 / lk. 6-11

Model synthesis from VHDL for the functional test generation systemKrupnova, Helena1993 https://www.ester.ee/record=b2090509*est

Modeling and simulation of circuits with shared structurally synthesized BDDsUbar, Raimund-Johannes; Jürimägi, Lembit; Raik, Jaan; Viies, VladimirMicroprocessors and microsystems2017 / p. 56-61 : ill http://dx.doi.org/10.1016/j.micpro.2016.09.006

Open source on-chip logic analyzer for FPGA-sEhrenpreis, Lauri; Ellervee, Peeter; Tammemäe, KalleBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 99-102 : ill

Operatsioonautomaadid digitaalarvutites : metoodiline materjal1987 https://www.ester.ee/record=b1234461*est

Parallel processing in FPGA-based digital circuits and systemsSklyarov, Valery; Skliarova, Iouliia2013 http://www.ester.ee/record=b2946103*est

Performance evaluation for FPGA-based processing of tree-like structuresSklyarov, Valery; Skliarova, Iouliia; Mihhailov, Dmitri; Sudnitsõn, Aleksander19th IEEE International Conference on Electronics, Circuits, and Systems (IEEE ICECS), Sevilla, Spain, December 9-12, 20122012 / p. 217-220 : ill https://ieeexplore.ieee.org/document/6463762

Programmeeritavad loogikaelemendidRoasto, IndrekElektriala2006 / 1, lk. 24-26 : ill

Resynthesis-based attacks against logic lockingAlmeida, Felipe; Aksoy, Levent; Nguyen, Quang-Linh; Dupuis, Sophie; Flottes, Marie-Lise; Pagliarini, Samuel Nascimento24 International Symposium on Quality Electronic Design, San Francisco, 5-7 April 20232023 / 8 p. : ill https://doi.org/10.1109/ISQED57927.2023.10129403 Article at Scopus Article at WOS

3D parallel fault simulationGorev, Maksim; Ubar, Raimund-JohannesProceedings of the 8th Annual Conference of the Estonian National Doctoral School in Information and Communication Technologies : December 5-6, 2014, Rakvere2014 / p. 39-42 : ill

Translating behavioral VHDL for emulationEllervee, Peeter; Reinsalu, Uljana; Arhipov, Anton25th IEEE NORCHIP Conference : Aalborg, Denmark, 19-20 November 20072007 / ? p https://ieeexplore.ieee.org/document/4481073

Алгоритм генерирования тестов для комбинационных логических схемPall, I.; Ubar, Raimund-JohannesXX студенческая научно-техническая конференция вузов Прибалтийских республик, Белорусской ССР и Молдавской ССР : тезисы докладов. Часть 11974 / с. 133 https://www.ester.ee/record=b1306141*est

Импульсные устройства : лабораторная работа No 5 : триггеры на логических элементах1988 https://www.ester.ee/record=b1224918*est

Метод дедуктивного анализа тестов для логических схемViilup, Agu; Kitsnik, Peeter; Ubar, Raimund-JohannesВопросы технической диагностики1977 / с. [?] https://www.ester.ee/record=b2353473*est

Метод сжатия диагностических словарей для логических схемSuga, M.; Ubar, Raimund-JohannesXX студенческая научно-техническая конференция вузов Прибалтийских республик, Белорусской ССР и Молдавской ССР : тезисы докладов. Часть 11974 / с.135-136 https://www.ester.ee/record=b1306141*est

О синтезе логических схем : автореферат ... кандидата физико-математических наукHanko, Piia1965 https://www.ester.ee/record=b1358931*est

О синтезе логических схем : диссертация на соискание ученой степени физико-математических наукHanko, Piia1964

Параллельное интерпретативное моделирование тестов для комбинационных логических схемPuntso, T.; Ubar, Raimund-JohannesXX студенческая научно-техническая конференция вузов Прибалтийских республик, Белорусской ССР и Молдавской ССР : тезисы докладов. Часть 11974 / с. 134 https://www.ester.ee/record=b1306141*est

Применение алгебры Буля при проектировании схем автоматики : конспект лекцийAgur, Ustus1974 https://www.ester.ee/record=b1292481*est

Разработка и исследование оптимизационных методов декомпозиционного синтеза управляющих автоматов в базисе программируемых логических устройств : автореферат ... кандидата технических наук (05.13.01)Berkman, Boriss1989 https://www.ester.ee/record=b1225548*est

Разработка и исследование оптимизационных методов декомпозиционного синтеза управляющих автоматов в базисе программируемых логических устройств : диссертация на соискание ученой степени кандидата технических наукBerkman, Boriss1989 https://www.ester.ee/record=b4636210*est

Система управления инвертором на диодтранзисторных логических элементахIrs, Rein; Pikkov, Otto; Šilf, K.; Tomson, Jaan; Šadeiko, T.Электромеханика. 31970 / с. 23-27 : илл https://www.ester.ee/record=b2189951*est https://digikogu.taltech.ee/et/Item/ba0097d6-af8f-4557-96a1-ac545e315074/

Управление процессами диагноза логических схемToome, T.; Ubar, Raimund-Johannes; Evartson, TeetТезисы докладов XXXI студенческой научно-технической конференции1980 / с. 55-57 https://www.ester.ee/record=b1319482*est