Acceleration of recursive data sorting over tree-based structuresMihhailov, Dmitri; Sudnitsõn, Aleksander; Sklyarov, Valery; Skliarova, IouliiaElektronika ir elektrotechnika = Electronics and electrical engineering2011 / p. 51-56 : ill https://eejournal.ktu.lt/index.php/elt/article/view/612

Algorithms of functional level testability analysis for digital circuitsUbar, Raimund-Johannes; Kuchcinski, KtzysztofPeriodica polytechnica. Electrical engineering1992 / 3/4, p. 295-308

Approaches to improve hierarchical ATPG for synchronous sequential circuitsViilukas, TaaviInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kuuenda aastakonverentsi artiklite kogumik : 3.-5. oktoobril 2012, Laulasmaa2012 / p. 105-108 : ill

Automated test pattern generator with constraint solverViilukas, Taavi; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / lk. 33-36

Boolean fault dignosis with structurally synthesized BDDsUbar, Raimund-JohannesRecent progress in the Boolean domain2014 / p. 303-331 : ill

Collaborative distributed computing in the field of digital electronics testingIvask, Eero; Devadze, Sergei; Ubar, Raimund-JohannesBalanced Automation Systems for Future Manufacturing Networks : 9th IFIP WG 5.5 International Conference : BASYS 2010 : Valencia, Spain, July 21-23, 2010 : proceedings2010 / p. 145-152

Collaborative distributed fault simulation for digital electronic circuitsIvask, Eero; Devadze, Sergei; Ubar, Raimund-JohannesIntelligent Distributed Computing IV : proceedings of the 4th International Symposium on Intelligent Distributed Computing - IDC 2010 : Tangier, Morocco, September 20102010 / p. 67-76

Constraint-based hierarchical untestability identification for synchronous sequential circuitsRaik, Jaan; Rannaste, Anna; Jenihhin, Maksim; Viilukas, Taavi; Ubar, Raimund-Johannes; Fujiwara, HideoSixteenth IEEE European Test Symposium : 23-27 May 2011, Trondheim2011 / p. 147-152

Constraint-based hierarchical untestability identification for syncronous sequential circuitsViilukas, Taavi; Raik, Jaan; Ubar, Raimund-Johannes; Rannaste, Anna; Jenihhin, Maksim; Fujiwara, HideoInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK viienda aastakonverentsi artiklite kogumik : 25.-26. novembril 2011, Nelijärve2011 / p. 139-142 : ill

Constraints solving based hierarchical test generation for synchronous sequential circuits = Kitsenduste lahendamisel baseeruv hierarhiline testigenereerimine sünkroonsetele järjestikskeemideleViilukas, Taavi2012 https://www.ester.ee/record=b2888278*est

Decision diagrams for diagnostic modelingUbar, Raimund-JohannesMEDIAN Finale : Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : November 10-11, 2015, Tallinn, Estonia2015 / p. 43

Defect-oriented modul-level fault diagnosis in digital circuitsKostin, Sergei; Ubar, Raimund-Johannes; Raik, JaanProceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 13-15, 2011, Gottbus, Germany2011 / p. 81-86

Description of digital objects with alternative graphs for test generation purposesUbar, Raimund-Johannes; Lohuaru, TõnuFault Tolerant Systems and Diagnostics : XI. International Conference ; Proceedings ; Suhl, June 6-9, 19881988 / p. [?]

Design and test technology for dependable systems-on-chip2011 https://www.ester.ee/record=b4467408*est

Design error diagnosis using backtrace algorithm on decision diagramsRepinski, Urmas; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, Maksim; Tšepurov, AntonInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / p. 93-96

Design obfuscation versus testFarahmandi, Farimah; Sinanoglu, Ozgur; Blanton, Ronald; Pagliarini, Samuel Nascimento2020 IEEE European Test Symposium (ETS) : ETS 2020, May 25 - 29, 2020, Tallinn, Estonia2020 / 10 p https://doi.org/10.1109/ETS48528.2020.9131590

Design of FPGA-based circuits using hierarchical finite state machinesSkliarova, Iouliia; Sklyarov, Valery; Sudnitsõn, Aleksander2012 http://www.ester.ee/record=b2857138*est

DfT-based external test and diagnosis of mesh-like networks on chips = Testitavusel põhinev välise testi ja diagnoosi meetod kahemõõtmelistele kiipvõrkudeleGovind, Vineeth2009 https://digi.lib.ttu.ee/i/?454 https://www.ester.ee/record=b2539211*est

Digital test in WEB-based environmentIvask, Eero2006 https://www.ester.ee/record=b2158119*est

Dynamic analysis of digital circuits with multi-valued simulationUbar, Raimund-JohannesMicroelectronics journal1998 / 11, p. 821-826: ill

Evalutionary two-criteria optimization of finite state machinesSpitšakova, MargaritaInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / lk. 101-104

Evolutionary approach to the functional test generation for digital circuitsSkobtsov, Y.A.; Ivanov, D.E.; Skobtsov, V.Y.; Ubar, Raimund-JohannesBEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia2004 / p. 229-232 : ill

Fast fault emulation for synchronous sequential circuitsRaik, Jaan; Ellervee, Peeter; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings of East–West Design & Test Workshop (EWDTW’04) : Yalta, Alushta, Crimea, Ukraine, September 23-26, 20042004 / p. 35-40 https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=a6eb712498a5f23db3f95ad66bada257c21e96f0

Fault collapsing in digital circuits using fast fault dominance and equivalence analysis with SSBDDsUbar, Raimund-Johannes; Jürimägi, Lembit; Orasson, Elmet; Raik, JaanVLSI-SoC : Design for Reliability, Security, and Low Power : 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 Daejeon, Korea, October 5-7, 2015 : revised selected papers2016 / p. 23-45 : ill http://dx.doi.org/10.1007/978-3-319-46097-0_2

Fault simulation of digital systems = Digitaalsüsteemide rikete simuleerimineDevadze, Sergei2009 https://digi.lib.ttu.ee/i/?445 https://www.ester.ee/record=b2508727*est

FPGA implementation of the polynomial curve fittingGorev, Maksim; Pesonen, VadimInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK viienda aastakonverentsi artiklite kogumik : 25.-26. novembril 2011, Nelijärve2011 / p. 121-124 : ill

FPGA-based fault emulation of synchronous sequential circuitsEllervee, Peeter; Raik, Jaan; Tammemäe, Kalle; Ubar, Raimund-JohannesIET computers and digital techniques2007 / 2, p. 70-76 : ill https://ieeexplore.ieee.org/abstract/document/1423822

FPGA-based implementation of EEG analyzerGorev, Maksim; Pesonen, Vadim; Mihhailov, Dmitri; Jenihhin, Maksim; Ellervee, PeeterDATE'11 Friday Workshop on "Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing" : Grenoble, France, March 20112011 / [1] p

FPGA-based systems in information and communicationSklyarov, Valery; Skliarova, Iouliia; Sudnitsõn, AleksanderAICT2011 : 5th International Conference on Application of Information and Communication Technologies : 12-14 October, Baku, Azerbaijan : conference proceedings2011 / p. 551-555

Functional level controllability analysis for digital circuitsUbar, Raimund-Johannes; Kuchcinski, KtzysztofProc. of the Design Automation Conference, Kaunas, Lithuania, June 1-4, 19921992 / p. 13-21

Functional self-test of high-performance pipe-lined signal processing architecturesGorev, Maksim; Ubar, Raimund-Johannes; Ellervee, Peeter; Devadze, Sergei; Raik, Jaan; Min, MartMicroprocessors and microsystems2015 / p. 909-918 : ill http://dx.doi.org/10.1016/j.micpro.2014.11.002

Hierarchical test generation for digital circuits represented by Decision Diagrams : thesis on informatics and system engineeringRaik, Jaan2001 https://www.ester.ee/record=b1578107*est

Hierarchical test pattern generation and untestability identification techniques for synchronous sequential circuits = Hierarhilised testintegreerimise ja mittetestitavuse identifitseerimise meetodid sünkroonsetele järjestikskeemideleRannaste, Anna2010 https://www.ester.ee/record=b2637391*est

Hierarhilisest testigenereerimisest ja mittetestitavuse analüüsistRannaste, AnnaA & A2010 / 4, lk. 38-39 https://artiklid.elnet.ee/record=b2286481*est

Hybrid built-in self-test : methods and tools for analysis and optimization of BIST = Sisseehitatud hübriidne isetestimine : meetodid ja vahendid analüüsiks ning optimeerimiseksOrasson, Elmet2007 https://www.ester.ee/record=b2305436*est

Improved fault emulation for synchronous sequential circuitsRaik, Jaan; Ellervee, Peeter; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 72-78 : ill

Investigation and development of test generation methods for control part of digital systemsBrik, Marina2002 http://www.ester.ee/record=b1688656*est

LFSR polynomial and seed selection using genetic algorithmAleksejev, E.; Jutman, Artur; Ubar, Raimund-JohannesBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 179-182 : ill

Logic simulation and fault collapsing with shared structurally synthesized BDDsMironov, Dmitri; Ubar, Raimund-Johannes; Raik, Jaan2014 19th IEEE European Test Symposium (ETS) : May 26th-30th, 2014, Paderborn, Germany : proceedings2014 / [2] p. : ill

Lower bounds of the size of shared structurally synthesized BDDsUbar, Raimund-Johannes; Mironov, DmitriProceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 23-25, 2014, Warsaw, Poland2014 / p. 77-82 : ill

Macro level defect-oriented diagnosability of digital circuitsKostin, Sergei; Ubar, Raimund-Johannes; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / lk. 53-56 : ill

Macro level defect-oriented diagnosability of digital circuitsKostin, Sergei; Ubar, Raimund-Johannes; Raik, JaanBEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia2010 / p. 149-152 : ill

Modeling sequential circuits with shared structurally synthesized BDDsUbar, Raimund-Johannes; Marenkov, Mihhail; Mironov, Dmitri; Viies, VladimirProceedings of 2014 9th International Design & Test Symposium (IDT) : Sheraton Club des Pins Hotel, Algiers, Algeria, December 16-18, 20142014 / p. 130-135 : ill

Multi-level test generation and fault diagnosis for finite state machinesUbar, Raimund-Johannes; Brik, MarinaDependable computing : proceedings / EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 19961996 / p. 264-281: ill

Multi-level test generation and fault diagnosis in digital systemsUbar, Raimund-Johannes1992

Multi-valued simulation of digital circuitsUbar, Raimund-JohannesProceedings : 1997 21st International Conference on Microelectronics :  Niš, Yugoslavia, 14-17 September 1997. Vol. 21997 / p. 721-724 : ill

New technique for hierarchical identification of untestable faults in sequential circuitsKrivenko, Anna; Ubar, Raimund-Johannes; Raik, Jaan; Kruus, MargusInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / lk. 155-158 : ill

A novel random approach to diagnostic test generationOsimiry, Emmanuel Ovie; Ubar, Raimund-Johannes; Kostin, Sergei; Raik, Jaan2nd IEEE NORCAS Conference : 1-2 November 2016, Copenhagen, Denmark2016 / [4] p. : ill https://doi.org/10.1109/NORCHIP.2016.7792915

Optimization of built-in self-test in digital systems = Sisseehitatud enesetestimise optimeerimine digitaalsüsteemidesKruus, Helena2011

Overview of the modular system for inference of finite state machinesSpitšakova, MargaritaInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK seitsmenda aastakonverentsi artiklite kogumik : 15.-16. novembril 2013, Haapsalu2013 / p. 95-98 : ill

Parallel processing in FPGA-based digital circuits and systemsSklyarov, Valery; Skliarova, Iouliia2013 http://www.ester.ee/record=b2946103*est

Practical works for on-line teaching design and test of digital circuitsJutman, Artur; Ubar, Raimund-Johannes; Hahanov, V.; Skvortsova, O.The 9th IEEE International Conference on Electronics, Circuits and Systems : ICECS 2002 : September 15-18, 2002, Dubrovnik, Croatia. Volume III2002 / p. 1223-1226 : ill http://dx.doi.org/10.1109/ICECS.2002.1046474

Representing logical inference steps with digital circuitsMatsak, ErikaHuman interface and the management of information : information and interaction2009 / p. 178-184 https://link.springer.com/chapter/10.1007/978-3-642-02559-4_20

Research on digital system design and test at Tallinn University of TechnologyUbar, Raimund-Johannes; Ellervee, Peeter; Hollstein, Thomas; Jervan, Gert; Jutman, Artur; Kruus, Margus; Raik, JaanResearch in Estonia : present and future2011 / p. 184-205 : ill

Riistvara kirjeldamiskeel - VHDL : metoodiline materjalTammemäe, Kalle2003 http://www.ester.ee/record=b1605950*est

Riistvara kirjeldamiskeel VHDL : metoodiline materjalTammemäe, Kalle2002 http://www.ester.ee/record=b1605950*est

Self-diagnosis in digital systems = Isediagnoosivad digitaalsüsteemidKostin, Sergei2012 https://www.ester.ee/record=b2757857*est

Sisseehitatud isetestimine digitaalsüsteemidesKruus, HelenaA & A2011 / lk. 32-37 : ill https://artiklid.elnet.ee/record=b2472216*est

Test program generation for microprocessor systemsDušina, Julia1993 https://www.ester.ee/record=b2090526*est

3D parallel fault simulationGorev, Maksim; Ubar, Raimund-JohannesProceedings of the 8th Annual Conference of the Estonian National Doctoral School in Information and Communication Technologies : December 5-6, 2014, Rakvere2014 / p. 39-42 : ill

True path tracing in structurally synthesized BDDs for testability analysis of
digital circuitsUbar, Raimund-Johannes; Jürimägi, Lembit; Oyeniran, Adeboye Stephen; Jenihhin, MaksimEuromicro Conference on Digital System Design : DSD 2019 : 28 - 30 August 2019
Kallithea, Chalkidiki, Greece : proceedings2019 / p. 492-499 : ill https://doi.org/10.1109/DSD.2019.00077

Using constraint solver in Test Pattern Generation ToolViilukas, Taavi; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / p. 14-17 : ill

Исследование и разработка методов управления поиском дефектов в цифровых схемах : автореферат .... кандидата технических наук (05.13.01)Evartson, Teet1986 https://www.ester.ee/record=b1301665*est

Оценка тенденции использования некоторых видов микросхемMaltsev, Jüri; Ševtšenko, S.Тезисы докладов республиканской научно-технической конференции, посвященной Дню радио. [1], Секция: Информационно-измерительная техника1981 / с. 25-26 https://www.ester.ee/record=b1310782~S1*est

Построение полных контролирующих тестов комбинационных схемUbar, Raimund-JohannesEesti NSV Teaduste Akadeemia toimetised. Füüsika. Matemaatika = Известия Академии наук Эстонской ССР. Физика. Математика = Proceedings of Academy of Sciences of the Estonian SSR. Physics. Mathematics1982 / lk. 418-427; ill. https://www.ester.ee/record=b1264310*est

Построение тестов цыфровых схем при помощи модели Алтернативных графовPlakk, Mari; Ubar, Raimund-JohannesАвтоматика и телемеханика1980 / с. 152-163 : илл https://www.ester.ee/record=b1515055*est

Проектирование контролепригодных дискретных систем : учебное пособиеUbar, Raimund-Johannes1988 https://www.ester.ee/record=b1225400*est