A synthesis-agnostic behavioral fault model for high gate-level fault coverageKarputkin, Anton; Raik, JaanProceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) : 14-18 March 2016, ICC, Dresden, Germany2016 / p. 1124-1127 : ill https://ieeexplore.ieee.org/document/7459477/figures#figures

Automated correction of design errors by edge redirection on high-level decision diagramsKarputkin, Anton; Ubar, Raimund-Johannes; Tombak, Mati; Raik, Jaan13th International Symposium on Quality Electronic Design (ISQED), 20122012 / p. 686-693 : ill https://ieeexplore.ieee.org/document/6113980

Canonical representations of high-level decision diagramsKarputkin, Anton; Ubar, Raimund-Johannes; Raik, Jaan; Tombak, MatiEstonian journal of engineering2010 / 1, p. 39-55 : ill

Formal verification and error correction on high-level decision diagrams = Formaalne verifitseerimine ja vigade parandamine kõrgtasemelistel otsustusdiagrammidelKarputkin, Anton2012

Generating directed tests for C programs using RTL ATPGRaik, Jaan; Drenkhan, Tiia; Jenihhin, Maksim; Viilukas, Taavi; Karputkin, Anton; Tšepurov, Anton; Ubar, Raimund-JohannesProceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)2012 / p. 1-6

High level decision diagrams and characteristic polynomialsKarputkin, AntonInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK viienda aastakonverentsi artiklite kogumik : 25.-26. novembril 2011, Nelijärve2011 / p. 143-146 : ill

Identifying untestable faults in sequential circuits using test path constraintsViilukas, Taavi; Karputkin, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Fujiwara, HideoJournal of electronic testing : theory and applications (JETTA)2012 / p. 511-521 : ill

Interactive presentation abstract : automated correction of design errors by edge redirection on high-level decision diagrams [Electronic resource]Karputkin, Anton; Ubar, Raimund-Johannes; Tombak, Mati; Raik, JaanIEEE International High Level Design Validation and Test Workshop (HLDVT'11), November 9-11, 2011, Napa Valley, CA2011 / p. 83 : ill. [CD-ROM] http://doi.ieeecomputersociety.org/10.1109/HLDVT.2011.6113980

Probabilistic equivalence checking based on high-level decision diagramsKarputkin, Anton; Ubar, Raimund-Johannes; Tombak, Mati; Raik, JaanProceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 13-15, 2011, Gottbus, Germany2011 / p. 423-428 : ill

Synthesis of high-level decision diagrams for functional test pattern generationUbar, Raimund-Johannes; Raik, Jaan; Karputkin, Anton; Tombak, MatiProceedings of the 16th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2009 : Lodz, Poland, 25-27 June, 20092009 / p. 519-524 : ill

Verification and error correction on High-Level Decision DiagramsKarputkin, Anton2013