A new testability calculation method to guide RTL test generationRaik, Jaan; Nõmmeots, Tanel; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications2005 / 1, p. 71-82 : ill https://link.springer.com/article/10.1007/s10836-005-5288-5

Application of high-level decision diagrams for simulation-based verification tasksJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesEstonian journal of engineering2010 / 1, p. 56-77 : ill

Application of structurally synthesized binary decision diagrams for timing simulation of digital circuitsJutman, Artur; Ubar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering2001 / 4, p. 269-288 : ill

Assertion checking with PSL and high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesDigest of papers IEEE 8th Workshop on RTL and High Level Testing : WRTLT'07 : October 12-13, 2007, Beijing, China2007 / p. 105-110 : ill https://pld.ttu.ee/~maksim/phd_papers/%5B12%5D%20wrtlt%2707.pdf

Automated correction of design errors by edge redirection on high-level decision diagramsKarputkin, Anton; Ubar, Raimund-Johannes; Tombak, Mati; Raik, Jaan13th International Symposium on Quality Electronic Design (ISQED), 20122012 / p. 686-693 : ill https://ieeexplore.ieee.org/document/6113980

Automated design error debug using high-level decision diagrams and mutation operatorsRaik, Jaan; Repinski, Urmas; Tšepurov, Anton; Hantson, Hanno; Ubar, Raimund-Johannes; Jenihhin, MaksimMicroprocessors and microsystems2013 / p. 505-513 : ill

Automated software-based self-test generation for microprocessorsJasnetski, Artjom; Ubar, Raimund-Johannes; Tšertov, AntonProceedings of the 24st International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2017 : Bydgoszcz, Poland, June 19-21, 20142017 / p. 453-458 : ill https://doi.org/10.23919/MIXDES.2017.8005252

Automatic generation of EFSMs and HLDDs for functional ATPGTšepurov, Anton; Guglielmo, Giuseppe di; Raik, Jaan; Ubar, Raimund-Johannes; Viilukas, TaaviBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 143-146 : ill

Canonical representations of high-level decision diagramsKarputkin, Anton; Ubar, Raimund-Johannes; Raik, Jaan; Tombak, MatiEstonian journal of engineering2010 / 1, p. 39-55 : ill

Code coverage analysis on high level decision diagramsReinsalu, UljanaInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 56-59 : ill

Decision diagrams - from a mathematical notion to engineering applicationsStankovic, Radomir S.; Ubar, Raimund-Johannes; Astola, JaakkoFacta Universitatis [Niš]. Series electronics and energetics2011 / p. 281-301 : ill http://dx.doi.org/10.2298/FUEE1103281S

Decision diagrams and digital testUbar, Raimund-Johannes41th International Conference on Microelectronics, Devices and Materials : MIDEM 2005 : Ribno at Bled, Slovenia : invited plenary paper2005 / p. 15-26

Decision diagrams for diagnostic modelingUbar, Raimund-JohannesMEDIAN Finale : Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : November 10-11, 2015, Tallinn, Estonia2015 / p. 43

Dependability evaluation in fault-tolerant systems with high-level decision diagramsUbar, Raimund-Johannes; Jervan, Gert; Raik, Jaan; Jenihhin, Maksim; Ellervee, PeeterComputer Science Meets Automation : 10-13 September 2007 : proceedings. Volume II2007 / p. 147-152 : ill https://www.db-thueringen.de/receive/dbt_mods_00008864

Design error diagnosis using backtrace algorithm on decision diagramsRepinski, Urmas; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, Maksim; Tšepurov, AntonInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / p. 93-96

Diagnostic modeling of digital systems with low- and high-level decision diagramsUbar, Raimund-JohannesLATW2013 : 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013 : [proceedings]2013 / [1] p

Diagnostic modeling of microprocessors with high-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, Maksim; Brik, Marina; Istenberg, Martin; Wuttke, Heinz-DietrichBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 147-150 : ill

Diagnostic modelling of digital systems with decision diagramsUbar, Raimund-JohannesВестник Томского государственного университета : приложение2004 / август, материалы международных, всесоюзных и региональных научных конференций, симпозиумов, школ, проводимых в ТГУ, с. 174-179 : ил

Diagnostic modelling of digital systems with multi-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Evartson, Teet; Kruus, Margus; Lensen, HarriProceedings of the 17th IASTED International Conference on Modelling and Simulation : May 24-26, 2006, Montreal, Quebec, Canada2006 / p. 207-212 : ill

Digitaalsüsteemide diagnostika Tallinna TehnikaülikoolisUbar, Raimund-JohannesTeadusmõte Eestis : tehnikateadused2002 / lk. 107-113 : ill

Equivalent transformations of structurally synthesized BDDs and applicationsJürimägi, Lembit; Ubar, Raimund-Johannes; Viies, Vladimir2019 8th Mediterranean Conference on Embedded Computing (MECO)2019 / 6 p. : ill https://doi.org/10.1109/MECO.2019.8760283

Fault effect reasoning in digital systems by topological view on low- and high-level decision diagramsUbar, Raimund-JohannesВестник Томского государственного университета. Управление, вычислительная техника и информатика2014 / p. 99-113 : ill http://journals.tsu.ru/informatics/&journal_page=archive&id=923&article_id=12107

Fault simulation and code coverage analysis of RTL designs using high-level decision diagrams = Rikete simuleerimine ja koodikatte analüüs register-siirde tasemel kasutades kõrgtaseme otsustusdiagrammeReinsalu, Uljana2013 https://www.ester.ee/record=b2963595*est

Fault simulation with parallel critical path tracing for combinational circuits using structurally synthesized BDDsDevadze, Sergei; Raik, Jaan; Jutman, Artur; Ubar, Raimund-Johannes7th IEEE Latin American Test Workshop LATW'06 : Buenos Aires, Argentina, March 26th-29th, 2006 : proceedings2006 / p. 97-102 : ill

Formal verification and error correction on high-level decision diagrams = Formaalne verifitseerimine ja vigade parandamine kõrgtasemelistel otsustusdiagrammidelKarputkin, Anton2012

High level decision diagrams and characteristic polynomialsKarputkin, AntonInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK viienda aastakonverentsi artiklite kogumik : 25.-26. novembril 2011, Nelijärve2011 / p. 143-146 : ill

High-level decision diagram based fault models for targeting FSMsRaik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi9th EUROMICRO Conference on Digital Systems Design : Architectures, Methods and Tools (DSD 2006) : 30 August 2006-1 September 2006, Cavtat near Dubrovnik, Croatia : proceedings2006 / p. 353-358 : ill http://dx.doi.org/10.1109/DSD.2006.60

High-Level Decision Diagram manipulations for code coverage analysisMinakova, Karina; Reinsalu, Uljana; Tšepurov, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Ellervee, PeeterBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 207-210 : ill

High-level decision diagrams based coverage metrics for verification and testJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesLATW 2009 : 10th IEEE Latin American Test Workshop : Buzios, Rio de Janero, Brazil, March 2-5, 20092009 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2009.4813792

High-level design error diagnosis using backtrace on decision diagramsRaik, Jaan; Repinski, Urmas; Ubar, Raimund-Johannes; Jenihhin, Maksim; Tšepurov, Anton28th Norchip Conference : Tampere, Finland, 15-16 November 2010 : conference program and papers2010 / [4] p. : ill http://dx.doi.org/10.1109/NORCHIP.2010.5669486

How to generate high quality tests for digital systemsUbar, Raimund-Johannes; Aarna, Margit; Kruus, Helena; Raik, Jaan2004 International Semiconductor Conference : 27th edition, October 4-6, 2004, Sinaia, Romania : CAS 2004 proceedings. Volume 22004 / p. 459-462 : ill http://dx.doi.org/10.1109/SMICND.2004.1403048

Intelligent decision making approach for performance evaluation of a robot-based manufacturing cellKangru, Tavo; Riives, Jüri; Otto, Tauno; Pohlak, Meelis; Mahmood, KashifASME 2018 International Mechanical Engineering Congress and Exposition : Pittsburgh, Pennsylvania, USA, November 9–15, 20182018 / Paper No. IMECE2018-86666, pp. V002T02A092; 10 p. : ill http://doi.org/10.1115/IMECE2018-86666

Multi-level fault simulation of digital systems on decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaThe First IEEE International Workshop on Electronic Design, Test and Applications : DELTA 2002, 29-31 January 2002, Christchurch, New Zealand : proceedings2002 / p. 86-91 : ill

Multiple fault testing in systems-on-chip with high-level decision diagramsUbar, Raimund-Johannes; Oyeniran, Adeboye Stephen; Schölzel, Mario; Vierhaus, Heinrich TheodorProceedings of 2015 10th International Design & Test Symposium (IDT) : Dead Sea, Jordan, 14-16 December 20152015 / p. 66-71 : ill http://dx.doi.org/10.1109/IDT.2015.7396738

Multi-valued simulation of digital circuits with structurally synthesized binary decision diagramsUbar, Raimund-JohannesMultiple valued logic. Vol. 41998 / p. 141-157

New fault models and self-test generation for microprocessors using High-Level Decision DiagramsJasnetski, Artjom; Raik, Jaan; Tšertov, Anton; Ubar, Raimund-Johannes2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings2015 / p. 251-254 : ill

On automatic software-based self-test program generation based on high-Level decision diagramsJasnetski, Artjom; Ubar, Raimund-Johannes; Tšertov, AntonLATS 2016 : 17th IEEE Latin-American Test Symposium, Foz do Iguacu, Brazil, 6th-9th April 20162016 / p. 177 http://dx.doi.org/10.1109/LATW.2016.7483357

Overview about low-level and high-level decision diagrams for diagnostic modeling of digital systemsUbar, Raimund-JohannesFacta Universitatis [Niš]. Series electronics and energetics2011 / p. 303-324 : ill http://dx.doi.org/10.2298/FUEE1103303U

Overview about low-lewel and high-level decision diagrams for diagnostic modeling of digital systemsUbar, Raimund-JohannesProceedings of the Reed-Muller 2011 Workshop : May 25-26, 2011, Tuusula, Finland2011 / p. 1-10 : ill

Parallel fault analysis on structurally synthesized BDDsDevadze, Sergei; Ubar, Raimund-JohannesInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 47-50 : ill

PSL assertion checking using temporally extended high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications2009 / 6, p. 289-300 : ill https://pld.ttu.ee/home/maksim/phd_papers/%5B11%5D%20latw%2708.pdf

PSL assertions based verification with HLDD toolsJenihhin, MaksimInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 17-20 : ill

Ranking strategic objectives in a strategy map based on logarithmic fuzzy preference programming and similarity methodSafari, Hossein; Khanmohammadi, Ehsan; Maleki, Meysam; Cruz-Machado, Virgilio; Ševtšenko, EduardManagement Systems in Production Engineering2019 / p. 153-161 : ill https://doi.org/10.1515/mspe-2019-0025 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Register-transfer level deductive fault simulation using decision diagramsReinsalu, Uljana; Raik, Jaan; Ubar, Raimund-JohannesBEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia2010 / p. 193-196 : ill

Simulation-based verification with APRICOT framework using high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesEast-West Design & Test Symposium : Moscow, September 18-21, 20092009 / p. 13-16 : ill

Software-based self-test generation for microprocessors with high-level decision diagramsJasnetski, Artjom; Ubar, Raimund-Johannes; Tšertov, Anton; Brik, MarinaProceedings of the Estonian Academy of Sciences2014 / p. 48-61 : ill

Software-based self-test generation for microprocessors with high-level decision diagramsUbar, Raimund-Johannes; Tšertov, Anton; Jasnetski, Artjom; Brik, MarinaLATW2014 : 15th IEEE Latin-American Test Workshop : Fortaleza, Brazil, March 12th-15th, 20142014 / [6] p. : ill

Software-based self-test with decision diagrams for microprocessorsUbar, Raimund-Johannes; Jasnetski, Artjom; Tšertov, Anton; Oyeniran, Adeboye Stephen2018

Structurally synthesized binary decision diagramsJutman, Artur; Peder, Ahti; Raik, Jaan; Tombak, Mati; Ubar, Raimund-JohannesBoolean Problems : 6th International Workshop : September 23-24, 2004, Freiberg2004 / p. 271-278 : ill

Structurally synthesized multiple input BDDs for simulation of digital circuitsUbar, Raimund-Johannes; Mironov, Dmitri; Raik, Jaan; Jutman, Artur16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009 : Yasmine Hammamet, Tunesia, 13-19 December, 20092009 / p. 451-454 : ill http://dx.doi.org/10.1109/ICECS.2009.5410895

Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generationLeveugle, R.; Ubar, Raimund-JohannesElectron technology1999 / 3, p. 282-287 : ill

Synthesis of high-level decision diagrams for functional test pattern generationUbar, Raimund-Johannes; Raik, Jaan; Karputkin, Anton; Tombak, MatiProceedings of the 16th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2009 : Lodz, Poland, 25-27 June, 20092009 / p. 519-524 : ill

Teaching diagnostic modeling of digital systems with decision diagrams [Electronic resource]Ubar, Raimund-Johannes; Raik, Jaan; Mironov, Dmitri; Evartson, Teet; Orasson, Elmet; Aarna, Margit; Wuttke, Heinz-DietrichProceedings of 12th IASTED International Conference on Computers and Advanced Technology in Education - CATE 2009 : St.Thomas, US, November 22-24, 20092009 / p. 1-6. [CD-ROM]

True path tracing in structurally synthesized BDDs for testability analysis of
digital circuitsUbar, Raimund-Johannes; Jürimägi, Lembit; Oyeniran, Adeboye Stephen; Jenihhin, MaksimEuromicro Conference on Digital System Design : DSD 2019 : 28 - 30 August 2019
Kallithea, Chalkidiki, Greece : proceedings2019 / p. 492-499 : ill https://doi.org/10.1109/DSD.2019.00077

Using test pattern generation tool decider in hardware verificationViilukas, Taavi; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 166-169 : ill

Verification and error correction on High-Level Decision DiagramsKarputkin, Anton2013