Application specific true critical paths identification in sequential circuitsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Oyeniran, Adeboye Stephen2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019) : 1-3 July 2019, Greece2019 / p. 299-304 : ill https://doi.org/10.1109/IOLTS.2019.8854442 Asynchronous fault detection in IEEE P1687 instrument networkShibin, Konstantin; Devadze, Sergei; Jutman, ArturIEEE 23rd North Atlantic Test Workshop : 14-16 May 2014, Binghampton, New York : proceedings2014 / p. 73-78 : ill At-speed self-testing of high-performance pipe-lined processing architectures [Electronic resource]Gorev, Maksim; Ubar, Raimund-Johannes; Ellervee, Peeter; Devadze, Sergei; Raik, Jaan; Min, Mart31st Norchip Conference : Vilnius, Lithuania, 11-12 November 2013 : conference program and papers2013 / p. 1-6 : ill [USB] Automatic SoC level test path synthesis based on partial functional modelsTšertov, Anton; Ubar, Raimund-Johannes; Jutman, Artur; Devadze, Sergei2011 Asian Test Symposium (ATS) : New Delhi, India2011 / p. 532-538 https://ieeexplore.ieee.org/document/6114730 Automation of testing beyond the SoCsTšertov, Anton; Jutman, Artur; Devadze, SergeiInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / lk. 29-32 : ill BASTION - board and SoC test instrumentation for Ageing and No Failure FoundDevadze, SergeiMEDIAN Finale : Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : November 10-11, 2015, Tallinn, Estonia2015 / p. 77 A benchmark suite for evaluating the efficiency of test toolsKruus, Helena; Ubar, Raimund-Johannes; Ellervee, Peeter; Gorev, Maksim; Pesonen, Vadim; Devadze, Sergei; Orasson, Elmet; Brik, Marina; Min, Mart; Annus, Paul; Kruus, Margus; Meigas, KaljuBEC 2012 : 2012 13th Biennial Baltic Electronics Conference : proceedings of the 13th Biennial Baltic Electronics Conference : October 3-5, 2012, Tallinn, Estonia2012 / p. 85-88 : ill Bringing research issues into lab scenarios on the example of SoC testing [Electronic resource]Ubar, Raimund-Johannes; Jutman, Artur; Devadze, Sergei; Wuttke, Heinz-DietrichInternational Conference on Engineering Education - ICEE 2007 : September 3-7, 2007, Coimbra, Portugal2007 / [7] p. : ill. [CD-ROM] http://icee2007.dei.uc.pt/proceedings/papers/429.pdf CMS drift tubes sector collector relocation phase 1 upgrade [Electronic resource]Bedoya, C. F.; Jutman, Artur; Shibin, Konstantin; Devadze, Sergei2015 http://cms.cern.ch/iCMS/jsp/openfile.jsp?type=DN&year=2015&files=DN2015_011.pdf Collaborative distributed computing in the field of digital electronics testingIvask, Eero; Devadze, Sergei; Ubar, Raimund-JohannesBalanced Automation Systems for Future Manufacturing Networks : 9th IFIP WG 5.5 International Conference : BASYS 2010 : Valencia, Spain, July 21-23, 2010 : proceedings2010 / p. 145-152 Collaborative distributed fault simulation for digital electronic circuitsIvask, Eero; Devadze, Sergei; Ubar, Raimund-JohannesIntelligent Distributed Computing IV : proceedings of the 4th International Symposium on Intelligent Distributed Computing - IDC 2010 : Tangier, Morocco, September 20102010 / p. 67-76 Combinational fault simulation in sequential circuitsUbar, Raimund-Johannes; Kõusaar, Jaak; Gorev, Maksim; Devadze, Sergei2015 IEEE International Symposium on Circuits and Systems : 24-27 May 2015, Lisboa, Portugal : [proceedings]2015 / p. 2876-2879 : ill Computer aided design support of FSM multiplicative decompositionSudnitsõn, Aleksander; Devadze, SergeiProceedings of the IEEE East-West Design & Test Workshop (EWDTW'06) : Sochi, Russia, September 15-19, 20062006 / p. 241-246 : ill Critical path tracing based simulation of transition delay faultsKõusaar, Jaak; Ubar, Raimund-Johannes; Devadze, Sergei; Raik, JaanProceedings of the 8th Annual Conference of the Estonian National Doctoral School in Information and Communication Technologies : December 5-6, 2014, Rakvere2014 / p. 61-66 : ill Critical path tracing based simulation of transition delay faultsKõusaar, Jaak; Ubar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan2014 17th Euromicro Conference on Digital System Design : DSD 2014 : 27-29 August 2014, Verona, Italy : proceedings2014 / p. 108-113 : ill DefSim - the defective ICPleskacz, Witold A.; Jutman, Artur; Ubar, Raimund-Johannes; Devadze, SergeiDATE 2007 : Design Automation and Test in Europe : Nice, France, April 16-20, 20072007 / p. s96 (2 p.) Designing reliable cyber-physical systemsAleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; Devadze, Sergei; Jenihhin, Maksim; Jutman, Artur; Raik, Jaan; Shibin, KonstantinLanguages, design methods, and tools for electronic system design : selected contributions from FDL 20162018 / p. 15-38 : ill https://doi.org/10.1007/978-3-319-62920-9_2 Conference Proceedings at Scopus Article at Scopus Designing reliable cyber-physical systems : overview associated to the special session at FDL'16Aleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; Devadze, Sergei; Jenihhin, Maksim; Jutman, Artur; Raik, Jaan; Shibin, KonstantinThe 2016 Forum on Specification & Design Languages : proceedings : Bremen, Germany, September 14-16, 20162016 / [8] p. : ill https://doi.org/10.1109/FDL.2016.7880382 Digital logic simulation with compressed BDDsUbar, Raimund-Johannes; Mironov, Dmitri; Devadze, Sergei; Raik, JaanProceedings : 2011 IEEE International Conference on Computer Science and Automation Engineering : June 10-12, 2011, Shanghai, China2011 / p. 105-109 : ill Distributed approach for parallel exact critical path tracing fault simulationIvask, Eero; Devadze, Sergei; Ubar, Raimund-JohannesMIXDES 2010 : 17th International Conference "Mixed Design of Integrated Circuits and Systems" : June 24-26, 2010, Wroclaw, Poland2010 / p. 471-476 : ill Distributed approach for parallel exact critical path tracing fault simulationIvask, Eero; Devadze, Sergei; Ubar, Raimund-JohannesInternational journal of microelectronics and computer science2010 / p. 165-174 : ill Distributed fault simulation with collaborative load balancing for VLSI circuitsIvask, Eero; Devadze, Sergei; Ubar, Raimund-JohannesScalable computing : practice and experience2011 / p. 153-163 : ill Effective scalable IEEE 1687 instrumentation network for fault managementJutman, Artur; Shibin, Konstantin; Devadze, SergeiIEEE design & test2013 / p. 26-35 : ill Efficient single-pattern fault simulation on structurally synthesized BDDsRaik, Jaan; Ubar, Raimund-Johannes; Devadze, Sergei; Jutman, ArturDependable Computing - EDCC-5 : 5th European Dependable Computing Conference : Budapest, Hungary, April 20-22, 2005 : proceedings2005 / p. 332-344 : ill E-learning environment for WEB-based study of testingUbar, Raimund-Johannes; Jutman, Artur; Raik, Jaan; Devadze, Sergei; Jenihhin, Maksim; Aleksejev, Igor; Tšepurov, Anton; Tšertov, Anton; Kostin, Sergei; Orasson, Elmet; Wuttke, Heinz-DietrichProceedings of the 8th European Workshop on Microelectronics Education : EWME 2010 : Darmstadt, Germany, 10-12 May 20102010 / p. 47-52 : ill E-learning tools for digital testDevadze, Sergei; Gorjachev, R.; Jutman, Artur; Orasson, Elmet; Rosin, Vjatšeslav; Ubar, Raimund-JohannesProc. III International Conference "Distance Learning - Educational Sphere of XXI Century" : Minsk, Belorussia, 20032003 / p. 336-342 Embedded instrumentation toolbox for screening marginal defects and outliers for productionOdintsov, Sergei; Jutman, Artur; Devadze, Sergei; Aleksejev, IgorIEEE AUTOTESTCON 2017 : Schaumburg, USA, Sept 11-14, 2017 : proceedings2017 / p. 336-334 : ill https://doi.org/10.1109/AUTEST.2017.8080516 Embedded synthetic instruments for board-level testingJutman, Artur; Devadze, Sergei; Aleksejev, Igor; Wenzel, ThomasProceedings : 2012 17th IEEE European Test Symposium (ETS) : May 28th–June 1st, 2012, Annecy, France2012 / 1 p. : ill Environment for the analysis of functional self-test quality in digital systemsUbar, Raimund-Johannes; Kostin, Sergei; Kruus, Helena; Aarna, Margit; Devadze, SergeiProceedings of the Estonian Academy of Sciences2014 / p. 151-162 : ill Exact parallel critical path fault tracing to speed-up fault simulation in sequential circuitsKõusaar, Jaak; Ubar, Raimund-Johannes; Kostin, Sergei; Devadze, Sergei; Raik, JaanInternational journal of microelectronics and computer science2018 / p. 9−18 https://ijmcs.dmcs.pl/web/guest/vol.-9-no.-1 https://ijmcs.dmcs.pl/documents/10630/345460/IJMCS_1_2018_2.pdf Fast extended test access via JTAG and FPGAsDevadze, Sergei; Jutman, Artur; Aleksejev, Igor; Ubar, Raimund-JohannesInternational Test Conference 2009 : November 1 - November 6, 2009, Austin Convention Center, Austin, Texas USA : proceedings2009 / p. 1-7 : ill http://dx.doi.org/10.1109/TEST.2009.5355668 Fast fault simulation for extended class of faults in scan-path circuitsUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, ArturProceedings : Fifth IEEE International Symposium on Electronic Design, Test and Applications : DELTA 2010 : 13-15 January 2010, Ho Chi Minh City, Vietnam2010 / p. 14-19 Fault management instrumentation network based on IEEE P1687 IJTAGShibin, Konstantin; Jutman, Artur; Devadze, SergeiEuropean Test Symposium (ETS), 2013, Avignon, France2013 Fault simulation of digital systems = Digitaalsüsteemide rikete simuleerimineDevadze, Sergei2009 https://digi.lib.ttu.ee/i/?445 https://www.ester.ee/record=b2508727*est Fault simulation with parallel critical path tracing for combinational circuits using structurally synthesized BDDsDevadze, Sergei; Raik, Jaan; Jutman, Artur; Ubar, Raimund-Johannes7th IEEE Latin American Test Workshop LATW'06 : Buenos Aires, Argentina, March 26th-29th, 2006 : proceedings2006 / p. 97-102 : ill Fault simulation with parallel exact critical path tracing in multiple core environmentGorev, Maksim; Ubar, Raimund-Johannes; Devadze, SergeiProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) : 9-13 March 2015, Grenoble, France2015 / p. 1180-1185 : ill FPGA-based embedded virtual instrumentation = FPGA-sisesed virtuaalsed test- ja mõõtevahendidAleksejev, Igor2013 http://www.ester.ee/record=b2927687*est FPGA-based synthetic instrumentation for board testAleksejev, Igor; Jutman, Artur; Devadze, Sergei; Odintsov, Sergei; Wenzel, ThomasProceedings : International Test Conference 20122012 / p. 1-10 : ill FSM decomposition software for education and researchDevadze, Sergei; Sudnitsõn, AleksanderProc. IEEE EUROCON 2005 International Conference on Computer as a tool : Belgrade, Serbia & Montenegro2005 / p. 839-842 Functional self-test of high-performance pipe-lined signal processing architecturesGorev, Maksim; Ubar, Raimund-Johannes; Ellervee, Peeter; Devadze, Sergei; Raik, Jaan; Min, MartMicroprocessors and microsystems2015 / p. 909-918 : ill http://dx.doi.org/10.1016/j.micpro.2014.11.002 Hardware/Software co-design in practice : MEMOCODE'08 contest experienceReinsalu, Uljana; Devadze, Sergei; Jutman, Artur; Tšertov, Anton; Ellervee, PeeterInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / p. 55-58 : ill Health management for self-aware SoCs based on IEEE 1687 infrastructureShibin, Konstantin; Devadze, Sergei; Jutman, Artur; Grabmann, Martin; Pricken, RobinIEEE Design & Test2017 / p. 27-35 : ill https://doi.org/10.1109/MDAT.2017.2750902 Hierarchical calculation of malicious faults for evaluating the fault-toleranceUbar, Raimund-Johannes; Devadze, Sergei; Jenihhin, Maksim; Raik, Jaan; Jervan, Gert; Ellervee, PeeterProceedings : Fourth IEEE International Symposium on Electronic Design, Test and Applications : [DELTA 2008] : 23-25 January 2008, Hong Kong, SAR, China2008 / p. 222-227 : ill Hierarchical timing-critical paths analysis in sequential circuitsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Kostin, Sergei2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain2018 / 6 p. : ill https://doi.org/10.1109/PATMOS.2018.8464176 High-speed logic level fault simulationUbar, Raimund-Johannes; Devadze, SergeiDesign and test technology for dependable systems-on-chip2011 / p. 310-335 : ill HLS-based optimization of tau triggering algorithm for LHC: a case studyCherezova, Natalia; Mihhailov, Dmitri; Devadze, Sergei; Jutman, Artur2022 18th Biennial Baltic Electronics Conference (BEC)2022 / 6 p. : ill https://doi.org/10.1109/BEC56180.2022.9935599 IEEE 1687 compliant ecosystem for embedded instrumentation access and in-field health monitoringTšertov, Anton; Jutman, Artur; Shibin, Konstantin; Devadze, SergeiIEEE AUTOTESTCON 2018 : National Harbor, September 17-20, 2018 : proceedings2018 / 9 p.: ill https://doi.org/10.1109/AUTEST.2018.8532559 IEEE P1687 IJTAG demonstrator on FPGAShibin, Konstantin; Aleksejev, Igor; Jutman, Artur; Devadze, SergeiDATE 2012 University Booth : Design Automation and Test in Europe : Dresden, Germany, March 12-16, 20122012 / 1 p. : ill In-system programming of non-volatile memories on microprocessor-centric boardsTšertov, Anton; Devadze, Sergei; Jutman, Artur; Jasnetski, ArtjomInternational journal of microelectronics and computer science2014 / p. 25-34 : ill Invited paper: System-Wide Fault Management based on IEEE P1687 IJTAGJutman, Artur; Devadze, Sergei; Aleksejev, Jevgeni6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) : 20-22 June 2011, Montpeillier, France2011 / [4] p.: ill Java technology based training system for teaching digital design and testDevadze, Sergei; Jutman, Artur; Sudnitsõn, Aleksander; Ubar, Raimund-Johannes; Wuttke, Heinz-DietrichBEC 2002 : proceedings of the 8th Biennial Baltic Electronics Conference : October 6-9, 2002, Tallinn, Estonia2002 / p. 283-286 : ill Learning digital test and diagnostics via internetUbar, Raimund-Johannes; Jutman, Artur; Kruus, Margus; Orasson, Elmet; Devadze, Sergei; Wuttke, Heinz-DietrichInternational journal of online engineering2007 / 1, [9] p. : ill https://www.db-thueringen.de/servlets/MCRFileNodeServlet/dbt_derivate_00032681/iJOE_1681-1221_03_2007_1_361.pdf Learning digital test and diagnostics via internet [Electronic resource]Ubar, Raimund-Johannes; Jutman, Artur; Kruus, Margus; Orasson, Elmet; Devadze, Sergei; Wuttke, Heinz-DietrichInternational journal of computing & information sciences2006 / 2, p. 86-96 : ill Marginal PCB assembly defect detection on DDR3/4 memory busOdintsov, Sergei; Jutman, Artur; Devadze, Sergei2017 IEEE International Test Conference (ITC 2017) : Forth Worth, Texas, USA, 31 October - 2 November 20172017 / p. 238-247 : ill https://doi.org/10.1109/TEST.2017.8242070 Microprocessor modeling for board level test access automationDevadze, Sergei; Jutman, Artur; Tšertov, Anton; Ubar, Raimund-JohannesProceedings of 10th IEEE Workshop on RTL and High Level Testing : Hong Kong, November 27-28, 20092009 / ? p Microprocessor-based system test using debug interfaceDevadze, Sergei; Jutman, Artur; Tšertov, Anton; Instenberg, Martin; Ubar, Raimund-Johannes26th Norchip Conference : Tallinn, Estonia, 17-18 November 2008 : formal proceedings2008 / p. 98-101 : ill http://dx.doi.org/10.1109/NORCHP.2008.4738291 On coverage of timing related faults at board levelJutman, Artur; Aleksejev, Igor; Devadze, Sergei2016 21st IEEE European Test Symposium (ETS) : May 23rd-26th 2016, Amsterdam, The Netherlands : proceedings2016 / [2] p. : ill https://doi.org/10.1109/ETS.2016.7519295 On in-system programming of non-volatile memoriesTšertov, Anton; Devadze, Sergei; Jutman, Artur; Jasnetski, ArtjomProceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2013, Gdynia, Poland, June 20-22, 20132013 / p. 408-413 : ill On in-system programming of non-volatile memoriesTšertov, Anton; Devadze, Sergei; Jutman, Artur; Jasnetski, ArtjomInternational journal of microelectronics and computer science2013 / p. 72-78 : ill On-line fault classification and handling in IEEE1687 based fault management system for complex SoCsShibin, Konstantin; Devadze, Sergei; Jutman, ArturLATS 2016 : 17th IEEE Latin-American Test Symposium, Foz do Iguacu, Brazil, 6th-9th April 20162016 / p. 69-74 : ill https://doi.org/10.1109/LATW.2016.7483342 Open-source JTAG simulator bundle for labsShibin, Konstantin; Devadze, Sergei; Rosin, Vjatšeslav; Jutman, Artur; Ubar, Raimund-JohannesInternational journal of electronics and telecommunications2012 / p. 233-239 : ill https://journals.pan.pl/Content/87192/PDF/32.pdf Optimization of boundary scan tests using FPGA-based efficient scan architecturesAleksejev, Igor; Devadze, Sergei; Jutman, Artur; Shibin, KonstantinJournal of electronic testing : theory and applications (JETTA)2016 / p. 245-255 : ill http://dx.doi.org/10.1007/s10836-016-5588-y Parallel critical path tracing fault simulation in sequential circuitsKõusaar, Jaak; Ubar, Raimund-Johannes; Kostin, Sergei; Devadze, Sergei; Raik, JaanProceedings of 25th International Conference MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS : MIXDES 2018 : Gdynia, Poland, June 21–23, 20182018 / p. 305-310 : ill https://doi.org/10.23919/MIXDES.2018.8436880 Parallel exact critical path tracing fault simulation with reduced memory requirementsDevadze, Sergei; Ubar, Raimund-Johannes; Raik, Jaan; Jutman, Artur4th International Conference on Design and Technology of Integrated Systems in Nanoscal Era : DTIS'09 : Cairo, Egypt, April 6-9, 20092009 / p. 155-160 : ill https://ieeexplore.ieee.org/document/4938046 Parallel fault analysis on structurally synthesized BDDsDevadze, Sergei; Ubar, Raimund-JohannesInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 47-50 : ill Parallel fault backtracing for calculation of fault coverageUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, ArturProceedings of the ASP-DAC 2008 : [13th] Asia and South Pacific Design Automation Conference 2008 : January 21-24, 2008, COEX, Seoul, Korea2008 / p. 667-672 : ill Parallel fault backtracing for calculation of fault coverageUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, Artur43rd International Conference on Microelectronics, Devices and Materials and the Workshop on Electronic Testing : September 12. - September 14.2007, Bled, Slovenia : MIDEM conference 2007 proceedings2007 / p. 165-170 : ill Parallel X-fault simulation with critical path tracing technique [Electronic resource]Ubar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, ArturDATE 10 : Design, Automation & Test in Europe : Dresden, Germany, 8-12 March, 20102010 / p. 879-884 [CD-ROM] Reliable health monitoring and fault management infrastructure based on embedded instrumentation and IEEE 1687Jutman, Artur; Shibin, Konstantin; Devadze, SergeiIEEE AUTOTESTCON 2016 : Anaheim, California, USA, September 12-15, 2016 : proceedings2016 / p. 240-249 : ill https://doi.org/10.1109/AUTEST.2016.7589605 Run-time reconfigurable instruments for advanced board-level testingAleksejev, Igor; Jutman, Artur; Devadze, SergeiIEEE AUTOTESTCON 2016 : Anaheim, California, USA, September 12-15, 2016 : proceedings2016 / p. 385-392 : ill https://doi.org/10.1109/AUTEST.2016.7589627 Run-time reconfigurable instruments for advanced board-level testingAleksejev, Igor; Jutman, Artur; Devadze, SergeiIEEE instrumentation & measurement magazine2017 / p. 23-30 : ill https://doi.org/10.1109/MIM.2017.8006390 SoC and board modeling for processor-centric board testingTšertov, Anton; Ubar, Raimund-Johannes; Jutman, Artur; Devadze, Sergei14th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : DSD 2011 : 31 August - 2 September 2011, Oulu, Finland : proceedings2011 / p. 575-582 : ill Software environment for synthesis of testable FSM through decompositionDevadze, Sergei; Sudnitsõn, Aleksander2008 26th International Conference on Microelectronics (MIEL 2008) : proceedings2008 / p. 433-436 Structurally synthesized multiple input BDDs for speeding up logic-level simulation of digital circuitsMironov, Dmitri; Ubar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, Artur13th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : DSD 2010 : Lille, France, 1-3 September 2010 : proceedings2010 / p. 658-663 : ill A suite of IEEE 1687 benchmark networksTšertov, Anton; Jutman, Artur; Devadze, Sergei2016 IEEE International Test Conference (ITC) : proceedings2016 / art. 6.1, p. 1-10 : ill https://doi.org/10.1109/TEST.2016.7805840 Synchronization, calibration and triggering of IEEE 1687 embedded instrumentsJutman, Artur; Devadze, Sergei; Shibin, KonstantinThe Seventeenth Workshop on RTL and High Level Testing (WRTLT'16) : November 24-25, 2016, Aki Grand Hotel, Hiroshima, Japan2016 / [6] p Synthesis of testable FSM through decompositionDevadze, Sergei; Sudnitsõn, AleksanderInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / p. 101-104 : ill System-wide fault management based on IEEE P1687 IJTAGShibin, Konstantin; Jutman, Artur; Devadze, SergeiInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kuuenda aastakonverentsi artiklite kogumik : 3.-5. oktoobril 2012, Laulasmaa2012 / p. 81-84 : ill Teaching digital RT-level self-test using a Java appletDevadze, Sergei; Jutman, Artur; Sudnitsõn, Aleksander; Ubar, Raimund-Johannes; Wuttke, Heinz-Dietrich20th IEEE NORCHIP Conference : Copenhagen, Denmark, November 11-12, 20022002 / p. 322-328 : ill Testing beyond the SoCs in a lego styleTšertov, Anton; Jutman, Artur; Devadze, SergeiProceedings of IEEE East-West Design & Test Symposium (EWDTS'10) : St. Petersburg, Russia, September 17-20, 20102010 / p. 334-338 : ill Trainer 1149: a boundary scan simulation bundle for labsJutman, Artur; Ubar, Raimund-Johannes; Devadze, Sergei; Shibin, Konstantin; Rosin, VjatšeslavMIXDES 2011 : 18th International Conference "Mixed Design of Integrated Circuits and Systems" : June 16-18, 2011, Gliwice, Poland2011 / p. 520-525 Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebraKõusaar, Jaak; Ubar, Raimund-Johannes; Devadze, Sergei; Raik, JaanMicroprocessors and microsystems2015 / p. 1130-1138 : ill http://dx.doi.org/10.1016/j.micpro.2015.05.003 Turning JTAG inside out for fast extended test accessDevadze, Sergei; Jutman, Artur; Aleksejev, Igor; Ubar, Raimund-Johannes10th IEEE Latin American Test Workshop : 2-5 March 2009, Brazil2009 / [6] p. : ill https://ieeexplore.ieee.org/document/4813799 Ultra fast parallel fault analysis on structurally synthesized BDDsUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, Artur12th IEEE European Test Symposium ETS 2007 : 20-24 May 2007, Freiburg, Germany : proceedings2007 / p. 131-136 : ill http://dx.doi.org/10.1109/ETS.2007.43 Understanding boundary scan test with Trainer 1149Jutman, Artur; Devadze, Sergei; Shibin, Konstantin; Rosin, Vjatšeslav; Ubar, Raimund-Johannes22nd EAEEIE annual conference : June, 13-15, 2011, Maribor, Slovenija : conference book2011 / p. 21-22 https://ieeexplore.ieee.org/document/6165727 Ways for board and system test to benefit from FPGA embedded instrumentationEhrenberg, Heiko; Odintsov, Sergei; Devadze, Sergei; Jutman, Artur; Aleksejev, Igor; Wenzel, Thomas2019 IEEE AUTOTESTCON2019 / 10 p : ill https://doi.org/10.1109/AUTOTESTCON43700.2019.8961057 Web based tools for synthesis and testing of digital devicesDevadze, Sergei; Jutman, Artur; Kruus, Margus; Sudnitsõn, Aleksander; Ubar, Raimund-JohannesProceedings of the International Conference on Computer Systems and Technologies (e-Learning) : CompSysTech'2002, Sofia, Bulgaria, 20-21 June2002 / p. 1.9-1 - 1.9-6 : ill Web-based computer aided design support of finite state machine additive decomposition for low powerSudnitsõn, Aleksander; Devadze, Sergei5th IEEE East-West Design & Test International Symposium2007 / p. 494-498 Web-based software implementation of finite state machine decomposition for design and educationDevadze, Sergei; Kruus, Margus; Sudnitsõn, AleksanderCompSysTech' 2001 : proceedings of the International Conference on Computer Systems and Technologies, Sofia, 21-22 June 20012001 / [6] p. : ill Web-based system for sequential machines decompositionDevadze, Sergei; Fomina, Jelena; Kruus, Margus; Sudnitsõn, AleksanderThe IEEE Region 8 EUROCON 2003 : Computer as a Tool : 22-24. September 2003, Ljubljana, Slovenia : proceedings. Volume A2003 / p. 57-61 : ill Web-based training system for teaching basics of RT-level digital design, test, and design for test [Electronic resource]Devadze, Sergei; Jutman, Artur; Sudnitsõn, Aleksander; Ubar, Raimund-Johannes9th International Conference MIXDES 2002 : Mixed Design of Integrated Circuits and Systems, Wroclaw, Poland, 20-22 June 20022002 / [6] p. : ill. [CD-ROM] Web-based training system for teaching digital design and testDevadze, Sergei7th International Student Conference on Electrical Engineering : POSTER2003 : May 22, 2003, Prague, Czech Republic2003 / p. IC6 Virtual reconfigurable scan-chains on FPGAs for optimized board testAleksejev, Igor; Jutman, Artur; Devadze, Sergei; Shibin, Konstantin2015 16th Latin American Test Symposium (LATS 2015) : Puerto Vallarta, Mexico, 25-27 March 20152015 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2015.7102411