A tool set for teaching design-for-testability of digital circuitsKostin, Sergei; Orasson, Elmet; Ubar, Raimund-JohannesEWME 2016 : 11th European Workshop on Microelectronics Education : May 11-13, 2016, Southampton, UK2016 / [6] p. : ill http://dx.doi.org/10.1109/EWME.2016.7496466

Accelerating transient fault injection campaigns by using Dynamic HDL SlicingBagbaba, Ahmet Cagri; Jenihhin, Maksim; Raik, Jaan; Sauer, Christian2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore2019 / 7 p. : ill https://doi.org/10.1109/NORCHIP.2019.8906932

Conditional fault collapsing in digital circuits with shared structurally synthesized BDDs [Online resource]Jürimägi, Lembit; Ubar, Raimund-JohannesBEC 2018 : 2018 16th Biennial Baltic Electronics Conference (BEC) : proceedings of the 16th Biennial Baltic Electronics Conference, October 8-10, 20182018 / 4 p. : ill https://doi.org/10.1109/BEC.2018.8600967

DeepAxe : a framework for exploration of approximation and reliability trade-offs in DNN acceleratorsTaheri, Mahdi; Riazati, Mohamad; Ahmadilivani, Mohammad Hasan; Jenihhin, Maksim; Daneshtalab, Masoud; Raik, Jaan; Sjödin, Mikael; Lisper, BjörnarXiv.org2023 / 8 p. : ill https://doi.org/10.48550/arXiv.2303.0822

Distributed approach for parallel exact critical path tracing fault simulationIvask, Eero; Devadze, Sergei; Ubar, Raimund-JohannesInternational journal of microelectronics and computer science2010 / p. 165-174 : ill

Distributed fault simulation with collaborative load balancing for VLSI circuitsIvask, Eero; Devadze, Sergei; Ubar, Raimund-JohannesScalable computing : practice and experience2011 / p. 153-163 : ill

Efficient fault injection based on dynamic HDL slicing techniqueBagbaba, Ahmet Cagri; Jenihhin, Maksim; Raik, Jaan; Sauer, Christian2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019) : 1-3 July 2019, Greece2019 / p. 52-53 : ill https://doi.org/10.1109/IOLTS.2019.8854419

Fast RTL fault simulation using decision diagrams and bitwise set operationsReinsalu, Uljana; Raik, Jaan; Ubar, Raimund-Johannes; Ellervee, Peeter2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : 3-5 October 2011, Vancouver, Canada2011 / p. 164-170

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanJournal of electronic testing : theory and applications2020 / p. 87-103 https://doi.org/10.1007/s10836-020-05856-7

High-level test data generation for software based self-test in microprocessorsOyeniran, Adeboye Stephen; Jasnetski, Artjom; Tšertov, Anton; Ubar, Raimund-Johannes2017 6th Mediterranean Conference on Embedded Computing (MECO) : including ECYPS'2017 : proceedings : research monograph : Bar, Montenegro, June 11th-15th, 20172017 / p. 86-91 : ill https://doi.org/10.1109/MECO.2017.7977167

Modeling sequential circuits with shared structurally synthesized BDDsUbar, Raimund-Johannes; Marenkov, Mihhail; Mironov, Dmitri; Viies, VladimirProceedings of 2014 9th International Design & Test Symposium (IDT) : Sheraton Club des Pins Hotel, Algiers, Algeria, December 16-18, 20142014 / p. 130-135 : ill

Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuitsUbar, Raimund-Johannes; Jürimägi, Lembit; Raik, Jaan2015 Nordic Circuits and Systems Conference (NORCAS) : NORCHIP & International Symposium on System-on-Chip (SoC) : 1st IEEE NORCAS Conference : 26-28 October 2015, Oslo, Norway2015 / [4] p. : ill http://dx.doi.org/10.1109/NORCHIP.2015.7364406

Teaching digital system testOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Kruus, MargusThe 27th EAEEIE Annual Conference : June 7-9, 2017, Grenoble2017 / [6] p