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1
A scalable model based RTL framework zamiaCAD for static analysis
Tšepurov, Anton
;
Jenihhin, Maksim
;
Raik, Jaan
;
Tihhomirov, Valentin
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) : October 7-10, 2012 Santa Cruz, USA Dream Inn, Santa Cruz, USA : [proceedings]
2012
/
p. 171-176 : ill
artikkel kogumikus
2
Accelerating transient fault injection campaigns by using Dynamic HDL Slicing
Bagbaba, Ahmet Cagri
;
Jenihhin, Maksim
;
Raik, Jaan
;
Sauer, Christian
2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore
2019
/
7 p. : ill
https://doi.org/10.1109/NORCHIP.2019.8906932
artikkel kogumikus
3
Efficient fault injection based on dynamic HDL slicing technique
Bagbaba, Ahmet Cagri
;
Jenihhin, Maksim
;
Raik, Jaan
;
Sauer, Christian
2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019) : 1-3 July 2019, Greece
2019
/
p. 52-53 : ill
https://doi.org/10.1109/IOLTS.2019.8854419
artikkel kogumikus
4
Extensible open-source framework for translating RTL VHDL IP cores to SystemC
Saif Abrar, Syed
;
Jenihhin, Maksim
;
Raik, Jaan
Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 8-10, 2013, Karlovy Vary, Czech Republic
2013
/
p. 112-115
artikkel kogumikus
5
Mutation analysis for systemC designs at TLM
Guarnieri, Valerio
;
Bombieri, Nicola
;
Pravadelli, Graziano
;
Fummi, Franco
;
Hantson, Hanno
;
Raik, Jaan
;
Jenihhin, Maksim
;
Ubar, Raimund-Johannes
12th IEEE Latin American Test Workshop (LATW) : Porto de Galinhas, Brasil, 27-30 March 2011
2011
/
[6] p
artikkel kogumikus
6
Simulation-based equivalence checking between IEEE 1687 ICL and RTL
Damljanovic, Aleksa
;
Jutman, Artur
;
Portolan, Michele
;
Tšertov, Anton
2019 IEEE International Test Conference (ITC)
2019
/
paper. 7.3, 8 p. : ill
https://doi.org/10.1109/ITC44170.2019.9000181
artikkel kogumikus
Kirjeid leitud 6, kuvan
1 - 6
pealkiri
23
1.
A new testability calculation method to guide RTL test generation
2.
A scalable model based RTL framework zamiaCAD for static analysis
3.
Abstraction of clock interface for conversion of RTL VHDL to SystemC
4.
An approach for verification assertions reuse 2 in RTL test pattern generation
5.
An approach for verification assertions reuse in RTL test pattern generation
6.
Automated design error localization in RTL designs
7.
Automatic synthesis of asynchronous circuits from synchronous RTL descriptions
8.
Comprehensive abstraction of VHDL RTL cores to ESL SystemC = Register-siirde taseme VHDL kirjelduste kompleksne abstraheerimine süsteemitaseme SystemC mudeliteks
9.
Early RTL analysis for SCA vulnerability in fuzzy extractors of memory-based PUF enabled devices
10.
Extensible open-source framework for translating RTL VHDL IP cores to SystemC
11.
Fast RTL fault simulation using decision diagrams and bitwise set operations
12.
Fault simulation and code coverage analysis of RTL designs using high-level decision diagrams = Rikete simuleerimine ja koodikatte analüüs register-siirde tasemel kasutades kõrgtaseme otsustusdiagramme
13.
From RTL liveness assertions to cost-effective hardware checkers
14.
FSMD RTL design manipulation for clock interface abstraction
15.
Generating directed tests for C programs using RTL ATPG
16.
On the reuse of TLM mutation analysis at RTL
17.
Open-source framework and practical considerations for translating RTL VHDL to SystemC
18.
Optimization methodologies for Cycle-Accurate SystemC models converted from RTL VHDL
19.
RTL assertion mining with automated RTL-to-TLM abstraction
20.
Simulation-based equivalence checking between IEEE 1687 ICL and RTL
21.
SystemC-based loose models : RTL abstraction for design understanding
22.
SystemC-based loose models for simulation speed-up by abstraction of RTL IP cores
23.
Using simulation statistics for bug localization in RTL designs
allikas
6
1.
Digest of papers : IEEE 11th Workshop on RTL and High Level Testing : WRTLT'10 : December 5-6, 2010, Shanghai, China
2.
Digest of papers IEEE 8th Workshop on RTL and High Level Testing : WRTLT'07 : October 12-13, 2007, Beijing, China
3.
Proceedings of 10th IEEE Workshop on RTL and High Level Testing : Hong Kong, November 27-28, 2009
4.
Proceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)
5.
The Ninth IEEE Workshop on RTL and High Level Testing (WRTLT 2008), Sapporo, Japan
6.
The Seventeenth Workshop on RTL and High Level Testing (WRTLT'16) : November 24-25, 2016, Aki Grand Hotel, Hiroshima, Japan
võtmesõna
3
1.
Register Transfer Level - RTL
2.
RTL
3.
RTL analysis