Layout to logic defect analysis for hierarchical test generation
author
Jenihhin, Maksim
Raik, Jaan
Ubar, Raimund-Johannes
Pleskacz, Witold A.
Rakowski, Michal
statement of authorship
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
source
Proceedings of the 2007 IEEE Workshop on Design and Diagnostic Circuits and Systems : April 11-13, 2007, Krakow, Poland
location of publication
[S.l.]
publisher
IEEE
year of publication
2007
pages
p. 35-40 : ill
conference name, date
10th IEEE Workshop on Design and Diagnostic Circuits and Systems, April 11-13, 2007
conference location
Krakow, Poland
url
http://dx.doi.org/10.1109/DDECS.2007.4295251
subject term
integraallülitused
lühis
notes
Bibliogr.: 17 ref
TalTech department
arvutitehnika instituut
language
inglise