Numerical scaling and speed-pover-optimization of polysilicon transistors & circuits
author
statement of authorship
Bubennikov A
location of publication
Tallinn
year of publication
pages
p. 41-46: ill
notes
Bibl. 10 ref
review
Kokkuvõte: Polüränitransistoride ja -lülituste numbriline skaleerimine ning nende toimekiiruse ja võimsuse optimiseerimine
language
inglise
subject term
Bubennikov, A. Numerical scaling and speed-pover-optimization of polysilicon transistors & circuits // Automation, simulation & measurement : ASM'91 : 3rd biennal conference, Tallinn, October 7-11, 1991. Section S / Tallinn Technical University. Tallinn, 1992. p. 41-46: ill.