Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems
author
Sklyarov, Valery
Skliarova, Iouliia
Rjabov, Artjom
Sudnitsõn, Aleksander
statement of authorship
Valery Sklyarov, Iouliia Skliarova, Artjom Rjabov, and Alexander Sudnitson
source
Proceedings of the Estonian Academy of Sciences
publisher
Estonian Academy Publishers
journal volume number month
vol. 66, 3
year of publication
2017
pages
p. 323-335 : ill
url
https://doi.org/10.3176/proc.2017.3.07
http://www.ester.ee/record=b2355998*est
subject term
andmed
arvuti arhitektuur
sortimine (informaatika)
riistvara
tarkvara
keyword
parallel data processing
merging
iterative networks
communication-time processing
Field-Programmable Gate Array (FPGA)
Peripheral Component Interconnect (PCI) express bus
ISSN
1736-6046
notes
Bibliogr.: 26 ref
Kokkuvõte: Kiired iteratiivsed ahelad ja RAM-i baasil ühendajad, kiirendamaks andmete sortimist riist- ning tarkvara süsteemides
Open Access
Open Access
scientific publication
teaduspublikatsioon
classifier
1.1
Scopus
https://www.scopus.com/sourceid/11500153303
https://www.scopus.com/record/display.uri?eid=2-s2.0-85028310572&origin=inward&txGid=f24c7d9e5835bb4d317ad67057afae88
WOS
https://jcr.clarivate.com/jcr-jp/journal-profile?journal=P%20EST%20ACAD%20SCI&year=2017
https://www.webofscience.com/wos/woscc/full-record/WOS:000408394600009
category (general)
Engineering
Tehnika
category (sub)
Engineering. General engineering
Tehnika. Üldine inseneriteadus
quartile
Q3
TalTech department
arvutisüsteemide instituut
language
inglise