Comprehensive performance and robustness analysis of 2D turn models for network-on-chips
author
Azad, Siavoosh Payandeh
Niazmand, Behrad
Janson, Karl
Kogge, Thilo
Raik, Jaan
Jervan, Gert
Hollstein, Thomas
statement of authorship
Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein
source
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
location of publication
Piscataway
publisher
IEEE
year of publication
2017
pages
p. 1476-1479 : ill
conference name, date
50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, 28.-31. May, 2017
conference location
Baltimore, United States
url
https://doi.org/10.1109/ISCAS.2017.8050634
subject term
kiipvõrgud
marsruutimine
algoritmid
Scopus
https://www.scopus.com/sourceid/56190
https://www.scopus.com/record/display.uri?eid=2-s2.0-85032697758&origin=inward&txGid=dda03cc1450744ab538f2e32b253fba8
WOS
https://www.webofscience.com/wos/woscc/full-record/WOS:000424890101140
quartile
Q3
category (general)
Engineering
Tehnika
category (sub)
Engineering. Electrical and electronic engineering
Tehnika. Elektri- ja elektroonikatehnika
keyword
turn model
routing algorithm
robustness
minimal path
network-on-chip
ISSN
2379-447X
0271-4310
ISBN
978-1-4673-6852-0
notes
bibliogr.: 13 ref
scientific publication
teaduspublikatsioon
classifier
3.1
TalTech department
arvutisüsteemide instituut
language
inglise