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Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler

author
Kerner, Madis
Tammemäe, Kalle
statement of authorship
Madis Kerner and Kalle Tammemae
source
Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany
location of publication
Piscataway
publisher
IEEE
year of publication
2017
pages
p. 92-95
conference name, date
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 19-21, 2017
conference location
Dresden, Germany
url
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553
subject term
tarkvaraarendus
hierarhilised struktuurid
konverentsikogumikud
tagasisidega juhtimissüsteemid
ISSN
2473-2117
ISBN
978-1-5386-0471-7
notes
Bibliogr.: 12 ref
TalTech department
arvutisüsteemide instituut
language
inglise
Kerner, M. Tammemäe, K. Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler // Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany. Piscataway : IEEE, 2017. p. 92-95. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553