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Processor vulnerability detection with the aid of assertions : RISC-V case study

author
Heidari Iman, Mohammad Reza
Ahmadi-Pour, Sallar
Drechsler, Rolf
Ghasempouri, Tara
statement of authorship
Mohammad Reza Heidari Iman, Sallar Ahmadi-Pour, Rolf Drechsler, Tara Ghasempouri
source
2024 IEEE Nordic Circuits and Systems Conference, NORCAS 2024 - Proceedings
location of publication
Piscataway, NJ
publisher
IEEE
year of publication
2024
pages
7 p.
conference name, date
2024 IEEE Nordic Circuits and Systems Conference (NORCAS), 29-30 October, 2024
conference location
Lund, Sweden
url
https:/doi.org/10.1109/NorCAS64408.2024.10752460
subject term
andmekaeve
verifikatsioon
protsessorid
riistvara
Scopus
Article at Scopus
WOS
Article at WOS
keyword
Automatic Security Verification
data mining
RISC-V processors
RISC-V security verification
security assertion mining
ISBN
979-833151766-3
notes
Bibliogr.: 38 ref
scientific publication
teaduspublikatsioon
classifier
3.1
TalTech department
arvutisüsteemide instituut
language
inglise
Heidari Iman, M.R., Ahmadi-Pour, S., Drechsler, R., Ghasempouri, T. Processor vulnerability detection with the aid of assertions : RISC-V case study // 2024 IEEE Nordic Circuits and Systems Conference, NORCAS 2024 - Proceedings. Piscataway, NJ : IEEE, 2024. 7 p.. https:/doi.org/10.1109/NorCAS64408.2024.10752460