Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation
author
Leveugle, R.
Ubar, Raimund-Johannes
statement of authorship
R. Leveugle, R. Ubar
source
Proceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 1998
location of publication
[S.l.]
year of publication
1998
pages
p. 353-358
url
https://hal.science/ccsd-00015077/
subject term
otsustusdiagrammid
süntees
VHDL (programmeerimiskeel)
testimine
language
inglise