An Accelerator-based architecture utilizing an efficient memory link for modern computational requirements
author
Yousefzadeh, Saba
Basharkhah, Katayoon
Raik, Jaan
Jenihhin, Maksim
statement of authorship
Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi
source
2019 IEEE East-West Design & Test Symposium (EWDTS)
location of publication
[S.l.]
publisher
IEEE
year of publication
2019
pages
6 p. : ill
conference name, date
2019 IEEE East-West Design & Test Symposium (EWDTS), 13-16 Sept. 2019
conference location
Batumi, Georgia
url
https://doi.org/10.1109/EWDTS.2019.8884481
subject term
manussüsteemid
kiirendid
heterogeensed süsteemid
keyword
heterogeneous systems
accelerator-based architecture
hardware accelerator
on-chip communication architectures
ISSN
2472-761X
2373-826X
ISBN
978-1-7281-1003-5
978-1-7281-1004-2
notes
Bibliogr.: 11 ref
TalTech department
arvutisüsteemide instituut
language
inglise
Reserch Group
Centre for trustworthy and efficient computing hardware (TECH)
Centre of dependable computing systems