Digital design flow with test activitiesDiener, Karl-Heinz; Elst, G.; Ivask, Eero; Jervan, Gert; Peng, Z.; Raik, Jaan; Ubar, Raimund-JohannesVILAB User Forum2000 / [11] p

FPGA design flow with automated test generationElst, G.; Diener, Karl-Heinz; Ivask, Eero; Raik, Jaan; Ubar, Raimund-JohannesProc. of German 11th Workshop on Test Technology and Reliability of Circuits and Systems : Potsdam, 19991999 / p. 120-123 https://masters.donntu.ru/2010/fknt/masyakin/library/article7.pdf

Internet-based testability-driven test generation in the virtual environment MOSCITOSchneider, Andre; Diener, Karl-Heinz; Elst, G.; Ivask, Eero; Raik, Jaan; Ubar, Raimund-JohannesInternational Federation for Information Processing IFIP : International Workshop on IP-Based SoC Design 2002 : proceedings : Grenoble, October 30-31, 20022002 / p. 357-362 : ill http://publica.fraunhofer.de/dokumente/N-287433.html

Virtual laboratory for research in dependable microelectronicsDiener, Karl-Heinz; Elst, G.; Gramatova, Elena; Kuzmicz, W.; Peng, Z.; Ubar, Raimund-JohannesThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 217-220 : ill

Построение тестов для проверки операционных частей дискретных системUbar, Raimund-Johannes; Lohuaru, Tõnu; Štraube, B.; Elst, G.Машинное проектирование электронных устройств и систем1988 / с. 65-77 : ил https://www.ester.ee/record=b1256708*est https://digikogu.taltech.ee/et/Item/2e6337b1-2222-4e66-98fb-89178f835390