Formalization of finite state machines with data path for the verification of high-level synthesisBorrione, Dominique; Dušina, Julia; Pierre, LaurenceXI Brasilian Symposium on Integrated Circuit Design, September 30 - October 3, 1998, Rio de Janeiro, Brazil : proceedings1998 / p. 99-102: ill

Generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault modelUbar, Raimund-Johannes; Borrione, DominiqueXI Brasilian Symposium on Integrated Circuit Design, September 30 - October 3, 1998, Rio de Janeiro, Brazil : proceedings1998 / p. 51-54