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Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation (title)
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journal article
Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation
Leveugle, R.
;
Ubar, Raimund-Johannes
Electron technology
1999
/
3, p. 282-287 : ill
journal article
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Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation
Leveugle, R.
;
Ubar, Raimund-Johannes
Proceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 1998
1998
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p. 353-358
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high-level decision diagrams (HLDD) synthesis
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