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journal article
Logic IP for low-cost IC design in advanced CMOS nodes
Isgenc, Mehmet Meric
;
Martins, Mayler G.A.
;
Zackriya, V. Mohammed
;
Pagliarini, Samuel Nascimento
;
Pileggi, Larry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2020
/
p. 585-595
https://doi.org//10.1109/TVLSI.2019.2942825
journal article
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keyword
50
1.
layout patterns
2.
facilities layout
3.
Layout
4.
Layout planning
5.
Layout Synthesis
6.
layout-based effects
7.
local layout effect (LLE)
8.
space layout
9.
warehouse layout
10.
abstract syntax patterns
11.
airflow patterns
12.
analysis patterns
13.
archetype patterns
14.
archetypes and archetype patterns
15.
archetypes and archetype patterns based development
16.
budgeting patterns
17.
business archetypes and archetype patterns
18.
consumer load patterns
19.
Damage patterns
20.
dark patterns
21.
demand patterns
22.
design patterns
23.
dietary patterns
24.
dive patterns
25.
dolphin patterns
26.
flow patterns
27.
human movement patterns
28.
identification patterns
29.
interaction patterns
30.
Leakage Patterns
31.
mining line patterns from event logs
32.
mining patterns from event logs
33.
model-based patterns
34.
moving patterns
35.
patterns
36.
polysemy patterns
37.
public behavior patterns
38.
religious patterns
39.
river flood patterns
40.
security patterns
41.
sequential patterns
42.
spatial patterns
43.
task knowledge patterns
44.
test patterns
45.
travel patterns
46.
trends and patterns
47.
trigger-response patterns
48.
urban patterns
49.
user interface patterns
50.
3D surface patterns
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