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Correct reuse of complex design units during high level synthesis : verification issues (title)
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Correct reuse of complex design units during high level synthesis : verification issues
Dušina, Julia
IEEE International High Level Design Validation and Test Workshop, Oakland, California, USA, November 15-16, 1996 : proceedings
1996
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6
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high level synthesis
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high-level decision diagrams (HLDD) synthesis
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high-level synthesis
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High-Level Synthesis (HLS)
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high-level synthesis for test
6.
logic level and high level BDDs
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