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2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : 3-5 October 2011, Vancouver, Canada (source)

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Fast RTL fault simulation using decision diagrams and bitwise set operationsReinsalu, Uljana; Raik, Jaan; Ubar, Raimund-Johannes; Ellervee, Peeter2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : 3-5 October 2011, Vancouver, Canada2011 / p. 164-170 https://ieeexplore.ieee.org/document/6104440

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