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• From virtual characterization to test-chips : DFM analysis through pattern enumerationMartins, Mayler G.A.; Pagliarini, Samuel Nascimento; Isgenc, Mehmet Meric; Pileggi, LarryIEEE transactions on computer-aided design of integrated circuits and systems2020 / p. 520-532 https://doi.org//10.1109/TCAD.2018.2889772
• Latch-Based logic lockingSweeney, J.; Mohammed Zackriya, V.; Pagliarini, Samuel Nascimento; Pileggi, LarryProceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, HOST 20202020 / p. 132−141 : ill https://doi.org/10.1109/HOST45689.2020.9300256
• Logic IP for low-cost IC design in advanced CMOS nodesIsgenc, Mehmet Meric; Martins, Mayler G.A.; Zackriya, V. Mohammed; Pagliarini, Samuel Nascimento; Pileggi, LarryIEEE Transactions on Very Large Scale Integration (VLSI) Systems2020 / p. 585-595 https://doi.org//10.1109/TVLSI.2019.2942825
• A probabilistic synapse with strained MTJs for Spiking Neural NetworksPagliarini, Samuel Nascimento; Bhuin, Sudipta; Isgenc, Mehmet Meric; Biswas, Ayan Kumar; Pileggi, LarryIEEE Transactions on Neural Networks and Learning Systems2020 / p. 1113-1123 : ill https://doi.org/10.1109/TNNLS.2019.2917819
• Split-chip design to prevent IP reverse engineeringPagliarini, Samuel Nascimento; Sweeney, Joseph; Mai, Ken; Blanton, Shawn; Mitra, Subhasish; Pileggi, LarryIEEE Design and Test2020 / p. 109-118 https://doi.org/10.1109/MDAT.2020.3033255 https://www.scopus.com/sourceid/21100286806 https://www.scopus.com/record/display.uri?eid=2-s2.0-85095985466&origin=inward&txGid=5cd9b065fa2590c9dd1c7c529d74978c https://jcr.clarivate.com/jcr-jp/journal-profile?journal=IEEE%20DES%20TEST&year=2022 https://www.webofscience.com/wos/woscc/full-record/WOS:000678331400021