• Exploiting high-level descriptions for circuits fault tolerance assessmentsBenso, A.; Prinetto, Paolo; Rebaudengo, M.; Sonza Reorda, Matteo; Raik, Jaan; Ubar, Raimund-Johannes1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, October 20-22, 19971997 / p. 212-216 https://ieeexplore.ieee.org/document/628327