Fey, G., Ghasempouri, T., Jacobs, S., Raik, J. et al.

full record print

Design understanding : from logic to specification

author

Fey, Goerschwin

Ghasempouri, Tara

Jacobs, Swen

Raik, Jaan

statement of authorship

Goerschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener

source

Proceedings of the 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) : October 8-10, 2018, Verona, Italy

publisher

IEEE

year of publication

2018

pages

p. 172–175 : ill

url

https://doi.org/10.1109/VLSI-SoC.2018.8644732

ISSN

2324-8440

2324-8432

ISBN

978-1-5386-4756-1

978-1-5386-4757-8

notes

Bibliogr.: 17 ref

scientific publication

teaduspublikatsioon

TTÜ department

arvutisüsteemide instituut

language

inglise

Märksõnad ja võtmesõnad

subject term

disain

arusaamine

hägusloogika

keyword

design understanding

temporal logics

specification

verification

synthesis

assertions

properties

Teaduspublikatsiooni meetrika

classifier

3.1

Reserch Group

Centre of dependable computing systems

Fey, G., Ghasempouri, T., Jacobs, S., Raik, J. et al. Design understanding : from logic to specification // Proceedings of the 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) : October 8-10, 2018, Verona, Italy. : IEEE, 2018. p. 172–175 : ill. https://doi.org/10.1109/VLSI-SoC.2018.8644732