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Processor vulnerability detection with the aid of assertions : RISC-V case study

author
Heidari Iman, Mohammad Reza
Ahmadi-Pour, Sallar
Drechsler, Rolf
Ghasempouri, Tara
statement of authorship
Mohammad Reza Heidari Iman, Sallar Ahmadi-Pour, Rolf Drechsler, Tara Ghasempouri
source
techrxiv.org
publisher
IEEE
year of publication
2024
pages
p. 1-8 : ill
url
https://doi.org/10.36227/techrxiv.172101134.45466090/v1
subject term
andmekaeve
verifikatsioon
protsessorid
riistvara
subject of form
preprindid
keyword
Automatic Security Verification
RISC-V Security Verification
Security Assertion Mining
Data Mining
notes
Bibliogr.: 36 ref
scientific publication
teaduspublikatsioon
classifier
6.7
TTÜ department
arvutisüsteemide instituut
language
inglise
Heidari Iman, M.R., Ahmadi-Pour, S., Drechsler, R., Ghasempouri, T. Processor vulnerability detection with the aid of assertions : RISC-V case study // techrxiv.org (2024), p. 1-8 : ill. https://doi.org/10.36227/techrxiv.172101134.45466090/v1