Abstraction of clock interface for conversion of RTL VHDL to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, Jaan2014 IEEE International Advance Computing Conference (IACC) : February 21-22, 2014, Gurgaon, India2014 / p. 50-55 : ill

Application specific processor synthesis from assembler code using VHDLUdre, JüriAsian-Pacific Conference on Hardware Description Langnages, Standards and Applications CAPCHDLSA-93, Australia1993

Application specific processor synthesis from assembler gode using VHDLTammemäe, Kalle; Udre, Jüri; Wehn, N.; Gasteier, M.; Glesner, M.APCHDLSA-93 Dec. 6-9, 19931993

Comprehensive abstraction of VHDL RTL cores to ESL SystemC = Register-siirde taseme VHDL kirjelduste kompleksne abstraheerimine süsteemitaseme SystemC mudeliteksAbrar, Syed Saif2016 http://www.ester.ee/record=b4564850*est

EEG analyzer prototype based on FPGAJenihhin, Maksim; Gorev, Maksim; Pesonen, Vadim; Mihhailov, Dmitri; Ellervee, Peeter; Hinrikus, Hiie; Bachmann, Maie; Lass, Jaanus7th International Symposium on Image and Signal Processing and Analysis (ISPA 2011) : September 4-6, 2011, Dubrovnik, Croatia : proceedings2011 / p. 101-106 : ill

Extensible open-source framework for translating RTL VHDL IP cores to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, JaanProceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 8-10, 2013, Karlovy Vary, Czech Republic2013 / p. 112-115

Formalization and validation of the std logic-1164 and numeric-std VHDL packages using the nqthm theorem proverDušina, Julia; Borrione, Dominique2nd Workshop on Libraries, Component Modeling and Quality Assurance : proceedings : Toledo, Spain, April, 19971997 / p. 169-180

Improved VHDL input for high-level synthesis tool xTractorEllervee, Peeter; Ivask, Eero; Kruus, MargusBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 87-90 : ill

Kas VHDL on sobiv keel sünteesiks?Tammemäe, KalleArvutustehnika ja Andmetöötlus1995 / 7, lk. 2-7; 8, lk. 8-14

Model synthesis from VHDL for the functional test generation systemKrupnova, Helena1993 https://www.ester.ee/record=b2090509*est

Optimization methodologies for Cycle-Accurate SystemC models converted from RTL VHDLSaif Abrar, Syed; Jenihhin, Maksim; Raik, JaanIP-SoC 2013 : IP embbeded system conference and exhibition : Grenoble, France, November 6-7, 20132013

Performance analysis of cosimulating processor core in VHDL and SystemCSaif Abrar, Syed; Shyam Kiran A.; Jenihhin, Maksim; Raik, Jaan; Babu, C.Proceedings of the 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI) : 22–25 August 2013, Mysore, India2013 / p. 563-568 : ill

Riistvara kirjeldamise keel VHDLTammemäe, KalleArvutustehnika ja Andmetöötlus1992 / 4, lk. 1-11: ill

Riistvara kirjeldamiskeel - VHDL : metoodiline materjal1992 https://www.ester.ee/record=b1062926*est

Riistvara kirjeldamiskeel - VHDL : metoodiline materjalTammemäe, Kalle2003 http://www.ester.ee/record=b1605950*est

Riistvara kirjeldamiskeel VHDL : metoodiline materjalTammemäe, Kalle2002 http://www.ester.ee/record=b1605950*est

Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generationLeveugle, R.; Ubar, Raimund-JohannesElectron technology1999 / 3, p. 282-287 : ill

Transforming VHDL descriptions from behavior to structureBerkman, Boriss; Sudnitsõn, Aleksander; Udre, JüriTallinna Tehnikaülikooli Toimetised1990 / lk. 27-44: ill

Translating behavioral VHDL for emulationEllervee, Peeter; Reinsalu, Uljana; Arhipov, Anton25th IEEE NORCHIP Conference : Aalborg, Denmark, 19-20 November 20072007 / ? p https://ieeexplore.ieee.org/document/4481073

VHDL based test generation systemJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 5th Electronic Devices and Systems Conference, Brno, June 11-12, 19981998 / p. 145-148

VHDL design debug framework based on zamiaCADTihhomirov, Valentin; Tšepurov, Anton; Saif Abrar, Syed; Jenihhin, Maksim; Raik, JaanDATE 2013 : Design Automation and Test in Europe, March 18-22, 2013, Grenoble, France2013 / [1] p. : ill

VHDL front-end for high-level synthesis tool xTractorIvask, Eero; Ellervee, PeeterBEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia2004 / p. 111-114 : ill

VHDL täna ja hommeTammemäe, KalleArvutustehnika ja Andmetöötlus1993 / 9, lk. 1-8