A scalable model based RTL framework zamiaCAD for static analysisTšepurov, Anton; Jenihhin, Maksim; Raik, Jaan; Tihhomirov, Valentin2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) : October 7-10, 2012 Santa Cruz, USA Dream Inn, Santa Cruz, USA : [proceedings]2012 / p. 171-176 : ill

A scalable technique to identify true critical paths in sequential circuitsUbar, Raimund-Johannes; Kostin, Sergei; Jenihhin, Maksim; Raik, JaanProceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany2017 / p. 152-157 : ill https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553

Abstraction of clock interface for conversion of RTL VHDL to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, Jaan2014 IEEE International Advance Computing Conference (IACC) : February 21-22, 2014, Gurgaon, India2014 / p. 50-55 : ill

Accelerating transient fault injection campaigns by using Dynamic HDL SlicingBagbaba, Ahmet Cagri; Jenihhin, Maksim; Raik, Jaan; Sauer, Christian2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore2019 / 7 p. : ill https://doi.org/10.1109/NORCHIP.2019.8906932

Accurate NBTI-induced gate delay modeling based on intensive SPICE simulationsKostin, Sergei; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, MaksimMEDIAN Finale : Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : November 10-11, 2015, Tallinn, Estonia2015 / p. 21-26 : ill

An Accelerator-based architecture utilizing an efficient memory link for modern computational requirementsYousefzadeh, Saba; Basharkhah, Katayoon; Raik, Jaan; Jenihhin, Maksim2019 IEEE East-West Design & Test Symposium (EWDTS)2019 / 6 p. : ill https://doi.org/10.1109/EWDTS.2019.8884481

An approach for PSL assertion coverage analysis with high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Shchenova, TatjanaProceedings of IEEE East-West Design & Test Symposium (EWDTS'10) : St. Petersburg, Russia, September 17-20, 20102010 / p. 13-16 : ill https://ieeexplore.ieee.org/document/5742048

An approach for verification assertions reuse 2 in RTL test pattern generationJenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi; Fujiwara, HideoJournal of Shanghai Normal University : Natural Sciences2010 / p. 441-447 : ill https://www.researchgate.net/publication/240613999_An_Approach_for_Verification_Assertions_Reuse_in_RTL_Test_Pattern_Generation

An approach for verification assertions reuse in RTL test pattern generationJenihhin, Maksim; Raik, Jaan; Fujiwara, Hideo; Ubar, Raimund-Johannes; Viilukas, TaaviDigest of papers : IEEE 11th Workshop on RTL and High Level Testing : WRTLT'10 : December 5-6, 2010, Shanghai, China2010 / p. 107-110 : ill

An optimization framework for dynamic pipeline management in computing systemsNaqvi, Syed Rameez; Zahid, Anjum; Sawalha, Lina; Jenihhin, MaksimComputers & electrical engineering2019 / p. 242-258 : ill https://doi.org/10.1016/j.compeleceng.2019.07.013 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Application of high-level decision diagrams for simulation-based verification tasksJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesEstonian journal of engineering2010 / 1, p. 56-77 : ill

Application specific true critical paths identification in sequential circuitsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Oyeniran, Adeboye Stephen2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019) : 1-3 July 2019, Greece2019 / p. 299-304 : ill https://doi.org/10.1109/IOLTS.2019.8854442

Applications of the open source HW design framework zamiaCADTšepurov, Anton; Tihhomirov, Valentin; Saif Abrar, Syed; Jenihhin, Maksim; Raik, JaanDATE 2012 University Booth : Design Automation and Test in Europe : Dresden, Germany, March 12-16, 20122012 / 1 p

Applying RIS-based communication for collaborative computing in a swarm of dronesRahbari, Dadmehr; Alam, Muhammad Mahtab; Le Moullec, Yannick; Jenihhin, MaksimIEEE Access2023 / p. 70093−70109 https://doi.org/10.1109/ACCESS.2023.3293737

APPRAISER : DNN fault resilience analysis employing approximation errorsTaheri, Mahdi; Ahmadilivani, Mohammad Hasan; Jenihhin, Maksim; Raik, Jaan; Daneshtalab, Masoud26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, May 3-5, 2023, Tallinn2023 / p. [?] https://ddecs2023.taltech.ee/

Approaches to extra-functional verification of security and reliability aspects in hardware designs = Riistvaraprojektide turva- ja töökindlusaspektide ekstrafunktsionaalse verifitseerimise lähenemisviisidLai, Xinhui2022 https://doi.org/10.23658/taltech.29/2022 https://digikogu.taltech.ee/et/Item/cff1aeb9-b0b2-49ce-b81a-bfb9dc25fd56 https://www.ester.ee/record=b5502807*est

APRICOT : a framework for teaching digital systems verificationRaik, Jaan; Jenihhin, Maksim; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-Johannes19th EAEEIE Annual Conference : June 29-July 2, 2008, Tallinn, Estonia : formal proceedings2008 / p. 172-177 : ill http://dx.doi.org/10.1109/EAEEIE.2008.4610181

Assertion checking with PSL and high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesDigest of papers IEEE 8th Workshop on RTL and High Level Testing : WRTLT'07 : October 12-13, 2007, Beijing, China2007 / p. 105-110 : ill https://pld.ttu.ee/~maksim/phd_papers/%5B12%5D%20wrtlt%2707.pdf

Assessment of diagnostic test for automated bug localizationTihhomirov, Valentin; Tšepurov, Anton; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-JohannesLATW2013 : 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013 : [proceedings]2013 / [6] p. : ill

Automated design error debug using high-level decision diagrams and mutation operatorsRaik, Jaan; Repinski, Urmas; Tšepurov, Anton; Hantson, Hanno; Ubar, Raimund-Johannes; Jenihhin, MaksimMicroprocessors and microsystems2013 / p. 505-513 : ill

Automated design error localization in RTL designsJenihhin, Maksim; Tšepurov, Anton; Tihhomirov, Valentin; Raik, Jaan; Hantson, Hanno; Ubar, Raimund-Johannes; Bartsch, Günter; Meza Escobar, Jorge Hernan; Wuttke, Heinz-DietrichIEEE design & test of computers2014 / p. 83-92 : ill http://dx.doi.org/10.1109/MDAT.2013.2271420

Automated identification of application-dependent safe faults in automotive systems-on-a-chipsBagbaba, Ahmet Cagri; Augusto da Silva, Felipe; Sonza Reorda, Matteo; Hamdioui, Said; Jenihhin, Maksim; Sauer, ChristianElectronics2022 / art. 319 https://doi.org/10.3390/electronics11030319 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

An automated method for mining high-quality assertion setsHeidari Iman, Mohammadreza; Raik, Jaan; Jenihhin, Maksim; Jervan, Gert; Ghasempouri, TaraMicroprocessors and microsystems2023 / art. 104773 https://doi.org/10.1016/j.micpro.2023.104773

Automated test bench generation for high-level synthesis flow ABELITEViilukas, Taavi; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Baranov, SamaryProceedings of IEEE East-West Design & Test Symposium (EWDTS'2011) : Sevastopol, Ukraine, September 9-12, 20112011 / p. 13-16 : ill https://ieeexplore.ieee.org/document/6116601

BASTION : board and SoC test instrumentation for ageing and no failure foundJutman, Artur; Lotz, Christophe; Larsson, Erik; Sonza Reorda, Matteo; Jenihhin, Maksim; Raik, JaanProceedings of the 2017 Design, Automation & Test in Europe (DATE) : 27-31 March 2017, Swisstech, Lausanne, Switzerland2017 / p. 115-120 : ill https://doi.org/10.23919/DATE.2017.7926968

Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanMicroprocessors and microsystems2020 / art. 103117, 12 p https://doi.org/10.1016/j.micpro.2020.103117 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Can a HW development and research environment be convenient, scalable and free? zamiaCAD : open-source platform for hardware design and analysis : [invited talk]Jenihhin, MaksimProceedings of IEEE East-West Design & Test Symposium (EWDTS’2012) : Kharkov, Ukraine, September 14–17, 20122012 / p. 548-549

Challenges of reliability assessment and enhancement in autonomous systemsJenihhin, Maksim; Sonza Reorda, Matteo; Balakrishnan, Aneesh; Alexandrescu, Dan2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2019)2019 / 6 p https://doi.org/10.1109/DFT.2019.8875379

Code coverage analysis for concurrent programming languages using high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesProceedings of the 12th European Workshop on Dependable Computing : EWDC 2009 : Toulouse, France, May 14-15, 20092009 / [4] p. : ill https://hal.archives-ouvertes.fr/hal-00381559

Code coverage analysis using high-level decision diagrams [Electronic resource]Raik, Jaan; Reinsalu, Uljana; Ubar, Raimund-Johannes; Jenihhin, Maksim; Ellervee, Peeter2008 IEEE Design and Diagnostics of Electronic Circuits and Systems : Bratislava, Slovakia, April 16-18, 20082008 / p. 201-207 : ill. [CD-ROM]

Combining dynamic slicing and mutation operators for ESL correctionRepinski, Urmas; Hantson, Hanno; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-JohannesProceedings : 2012 17th IEEE European Test Symposium (ETS) : May 28th-June 1st, 2012, Annecy, France2012 / [6] p. : ill

Composing graph theory and deep neural networks to evaluate SEU type soft error effectsBalakrishnan, Aneesh; Lange, Thomas; Glorieux, Maximilien; Alexandrescu, Dan; Jenihhin, Maksim9th Mediterranean Conference on Embedded Computing (MECO'2020), Budva, Montenegro, 8-11 June 20202020 https://doi.org/10.1109/MECO49872.2020.9134279

Comprehensive abstraction of VHDL RTL cores to ESL SystemC = Register-siirde taseme VHDL kirjelduste kompleksne abstraheerimine süsteemitaseme SystemC mudeliteksAbrar, Syed Saif2016 http://www.ester.ee/record=b4564850*est

Constraint-based hierarchical untestability identification for synchronous sequential circuitsRaik, Jaan; Rannaste, Anna; Jenihhin, Maksim; Viilukas, Taavi; Ubar, Raimund-Johannes; Fujiwara, HideoSixteenth IEEE European Test Symposium : 23-27 May 2011, Trondheim2011 / p. 147-152

Constraint-based hierarchical untestability identification for syncronous sequential circuitsViilukas, Taavi; Raik, Jaan; Ubar, Raimund-Johannes; Rannaste, Anna; Jenihhin, Maksim; Fujiwara, HideoInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK viienda aastakonverentsi artiklite kogumik : 25.-26. novembril 2011, Nelijärve2011 / p. 139-142 : ill

Constraint-based test pattern generation at the register-transfer levelViilukas, Taavi; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Krivenko, AnnaProceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 14-16, 2010, Vienna, Austria2010 / p. 352-357 : ill http://dx.doi.org/10.1109/DDECS.2010.5491752

CREDES Summer School : Dependable Systems Design : handouts2011 http://www.ester.ee/record=b2891192*est

DeepAxe : a framework for exploration of approximation and reliability trade-offs in DNN acceleratorsTaheri, Mahdi; Riazati, Mohamad; Ahmadilivani, Mohammad Hasan; Jenihhin, Maksim; Daneshtalab, Masoud; Raik, Jaan; Sjödin, Mikael; Lisper, BjörnarXiv.org2023 / 8 p. : ill https://doi.org/10.48550/arXiv.2303.0822

Dependability evaluation in fault-tolerant systems with high-level decision diagramsUbar, Raimund-Johannes; Jervan, Gert; Raik, Jaan; Jenihhin, Maksim; Ellervee, PeeterComputer Science Meets Automation : 10-13 September 2007 : proceedings. Volume II2007 / p. 147-152 : ill https://www.db-thueringen.de/receive/dbt_mods_00008864

Design error diagnosis using backtrace algorithm on decision diagramsRepinski, Urmas; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, Maksim; Tšepurov, AntonInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / p. 93-96

Designing reliable cyber-physical systemsAleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; Devadze, Sergei; Jenihhin, Maksim; Jutman, Artur; Raik, Jaan; Shibin, KonstantinLanguages, design methods, and tools for electronic system design : selected contributions from FDL 20162018 / p. 15-38 : ill https://doi.org/10.1007/978-3-319-62920-9_2 Conference Proceedings at Scopus Article at Scopus

Designing reliable cyber-physical systems : overview associated to the special session at FDL'16Aleksandrowicz, Gadi; Arbel, Eli; Bloem, Roderick; Devadze, Sergei; Jenihhin, Maksim; Jutman, Artur; Raik, Jaan; Shibin, KonstantinThe 2016 Forum on Specification & Design Languages : proceedings : Bremen, Germany, September 14-16, 20162016 / [8] p. : ill https://doi.org/10.1109/FDL.2016.7880382

A DFT scheme to improve coverage of hard-to-detect faults in FinFET SRAMsCardoso Medeiros, Guilherme; Gürsoy, Cemil Cem; Fieback, Moritz; Wu, Lizhou; Jenihhin, Maksim; Taouil, Mottaqiallah; Hamdioui, Said2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 9-13 March 2020, Grenoble, France : proceedings2020 / p. 792-797 https://doi.org/10.23919/DATE48585.2020.9116278

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysisHantson, Hanno; Repinski, Urmas; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-JohannesLATW 2012 : 13th IEEE Latin-American Test Workshop proceedings : April 10th-13th, 2012, Quito, Ecuador2012 / [6 p.] : ill

Diagnostic modeling of digital systems with multi-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, MaksimDesign and test technology for dependable systems-on-chip2011 / p. 92-118 : ill

Diagnostic modeling of microprocessors with high-level decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, Maksim; Brik, Marina; Istenberg, Martin; Wuttke, Heinz-DietrichBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 147-150 : ill

Diagnostic test generation for statistical bug localization using evolutionary computationGaudesi, Marco; Jenihhin, Maksim; Raik, Jaan; Tihhomirov, Valentin; Ubar, Raimund-JohannesApplications of Evolutionary Computation : 17th European Conference, EvoApplications 2014, Granada, Spain, April 23-25, 2014 : revised selected papers2014 / p. 425-436 : ill

Early RTL analysis for SCA vulnerability in fuzzy extractors of memory-based PUF enabled devicesLai, Xinhui; Jenihhin, Maksim; Selims, GeorgiosarXiv.org2020 / 6 p. : ill https://doi.org/10.48550/arXiv.2008.08409 https://arxiv.org/abs/2008.08409

Edge-to-Fog collaborative computing in a swarm of dronesRahbari, Dadmehr; Alam, Muhammad Mahtab; Le Moullec, Yannick; Jenihhin, MaksimAdvances in Model and Data Engineering in the Digitalization Era : MEDI 2021 International Workshops: DETECT, SIAS, CSMML, BIOC, HEDA, Tallinn, Estonia, June 21–23, 2021 : proceedings2021 / p. 78–87 https://doi.org/10.1007/978-3-030-87657-9_6 Conference Proceedings at Scopus Article at Scopus

EEG analyzer prototype based on FPGAJenihhin, Maksim; Gorev, Maksim; Pesonen, Vadim; Mihhailov, Dmitri; Ellervee, Peeter; Hinrikus, Hiie; Bachmann, Maie; Lass, Jaanus7th International Symposium on Image and Signal Processing and Analysis (ISPA 2011) : September 4-6, 2011, Dubrovnik, Croatia : proceedings2011 / p. 101-106 : ill

Efficient fault injection based on dynamic HDL slicing techniqueBagbaba, Ahmet Cagri; Jenihhin, Maksim; Raik, Jaan; Sauer, Christian2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019) : 1-3 July 2019, Greece2019 / p. 52-53 : ill https://doi.org/10.1109/IOLTS.2019.8854419

E-learning environment for WEB-based study of testingUbar, Raimund-Johannes; Jutman, Artur; Raik, Jaan; Devadze, Sergei; Jenihhin, Maksim; Aleksejev, Igor; Tšepurov, Anton; Tšertov, Anton; Kostin, Sergei; Orasson, Elmet; Wuttke, Heinz-DietrichProceedings of the 8th European Workshop on Microelectronics Education : EWME 2010 : Darmstadt, Germany, 10-12 May 20102010 / p. 47-52 : ill

Energy-efficient multi-fragment Markov model guided online model-based testing for MPSoCVain, Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Apneet Kaur; Jenihhin, Maksim; Raik, Jaan; Nõmm, SvenGreen IT Engineering: Social, Business and Industrial Applications2019 / p. 273-297 https://doi.org/10.1007/978-3-030-00253-4_12 Article collection at Scopus Article at Scopus

Estonia : e-Design and EDAJenihhin, Maksim50th DAC Global Forum2013 / [2] p

Extensible open-source framework for translating RTL VHDL IP cores to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, JaanProceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 8-10, 2013, Karlovy Vary, Czech Republic2013 / p. 112-115

Fast and fair computation offloading management in a swarm of drones using a rating-based federated learning approachRahbari, Dadmehr; Alam, Muhammad Mahtab; Le Moullec, Yannick; Jenihhin, MaksimIEEE Access2021 / p. 113832-113849 https://doi.org/10.1109/ACCESS.2021.3104117 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Fast identification of true critical paths in sequential circuitsUbar, Raimund-Johannes; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Jürimägi, LembitMicroelectronics reliability2018 / p. 252-261 : ill https://doi.org/10.1016/j.microrel.2017.11.027 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

FP7 DIAMOND : design error diagnosis and correction success storiesRaik, Jaan; Jenihhin, Maksim; Könighofer, RobertEuropean Test Symposium (ETS), 2013, Avignon, France2013 / p. 1-6

FPGA-based implementation of EEG analyzerGorev, Maksim; Pesonen, Vadim; Mihhailov, Dmitri; Jenihhin, Maksim; Ellervee, PeeterDATE'11 Friday Workshop on "Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing" : Grenoble, France, March 20112011 / [1] p

FSMD RTL design manipulation for clock interface abstractionAbrar, Syed Saif; Jenihhin, Maksim; Raik, Jaan2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI) : 10-13 August 2015, Kerala, India2015 / p. 463-468 : ill http://dx.doi.org/10.1109/ICACCI.2015.7275652

Gate-level graph representation learning : a step towards the improved stuck-at faults analysisBalakrishnan, Aneesh; Alexandrescu, Dan; Jenihhin, Maksim; Lange, Thomas; Glorieux, MaximilienProceedings of the Twenty Second International Symposium on Quality Electronic Design (ISQED) : Santa Clara, USA, 7-9 April 20212021 / p. 24-30 https://doi.org/10.1109/ISQED51717.2021.9424256

Gate-level modelling of NBTI-induced delays under process variationsCopetti, Thiago; Cardoso Medeiros, Guilherme; Bolzani Poehls, Leticia; Vargas, Fabian; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-JohannesLATS 2016 : 17th IEEE Latin-American Test Symposium, Foz do Iguacu, Brazil, 6th-9th April 20162016 / p. 75-80 : ill http://dx.doi.org/10.1109/LATW.2016.7483343

Generating directed tests for C programs using RTL ATPGRaik, Jaan; Drenkhan, Tiia; Jenihhin, Maksim; Viilukas, Taavi; Karputkin, Anton; Tšepurov, Anton; Ubar, Raimund-JohannesProceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)2012 / p. 1-6

Hardware modeling for design verification and debug = Riistvara modelleerimine disaini verifitseerimise ja silumise jaoksTšepurov, Anton2013 https://www.ester.ee/record=b2963501*est

Hierarchical analysis of short defects between metal lines in CMOS ICPleskacz, Witold A.; Jenihhin, Maksim; Raik, Jaan; Rakowski, Michal; Ubar, Raimund-Johannes; Kuzmicz, WieslawProceedings : 11th EUROMICRO Conference on Digital System Design : Architectures, Methods and Tools : (DSD 2008) : September 3-5, 2008, Parma, Italy2008 / p. 729-734 : ill

Hierarchical calculation of malicious faults for evaluating the fault-toleranceUbar, Raimund-Johannes; Devadze, Sergei; Jenihhin, Maksim; Raik, Jaan; Jervan, Gert; Ellervee, PeeterProceedings : Fourth IEEE International Symposium on Electronic Design, Test and Applications : [DELTA 2008] : 23-25 January 2008, Hong Kong, SAR, China2008 / p. 222-227 : ill

Hierarchical identification of NBTI-critical gates in nanoscale logicKostin, Sergei; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, MaksimLATW2014 : 15th IEEE Latin-American Test Workshop : Fortaleza, Brazil, March 12th-15th, 20142014 / [6] p. : ill

Hierarchical timing-critical paths analysis in sequential circuitsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Kostin, Sergei2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain2018 / 6 p. : ill https://doi.org/10.1109/PATMOS.2018.8464176

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan2019 IEEE European Test Symposium (ETS) : ETS 2019, May 27-31, 2019, Baden-Baden, Germany : Proceedings2019 / 6 p. : ill https://doi.org/10.1109/ETS.2019.8791526

High-level combined deterministic and pseudo-exhuastive test generation for RISC processorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Gürsoy, Cemil Cem; Raik, Jaan2019 IEEE European Test Symposium (ETS) : proceedings2019 / 6 p. : ill https://doi.org/10.1109/ETS.2019.8791526

High-Level Decision Diagram manipulations for code coverage analysisMinakova, Karina; Reinsalu, Uljana; Tšepurov, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Ellervee, PeeterBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 207-210 : ill

High-level decision diagram simulation for diagnosis and soft-error analysisRaik, Jaan; Repinski, Urmas; Jenihhin, Maksim; Chepurov, AntonDesign and test technology for dependable systems-on-chip2011 / p. 294-309 : ill

High-level decision diagrams based coverage metrics for verification and testJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesLATW 2009 : 10th IEEE Latin American Test Workshop : Buzios, Rio de Janero, Brazil, March 2-5, 20092009 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2009.4813792

High-level design error diagnosis using backtrace on decision diagramsRaik, Jaan; Repinski, Urmas; Ubar, Raimund-Johannes; Jenihhin, Maksim; Tšepurov, Anton28th Norchip Conference : Tampere, Finland, 15-16 November 2010 : conference program and papers2010 / [4] p. : ill http://dx.doi.org/10.1109/NORCHIP.2010.5669486

High-level fault diagnosis in RISC processors with Implementation-Independent Functional TestOyeniran, Adeboye Stephen; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) : Nicosia, Cyprus : 04-06 July 20222022 / p. 32-37 https://doi.org/10.1109/ISVLSI54635.2022.00019

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanJournal of electronic testing : theory and applications2020 / p. 87-103 https://doi.org/10.1007/s10836-020-05856-7

Holistic IJTAG-based external and internal fault monitoring in UAVsAhmed, Foisal; Jenihhin, MaksimarXiv.org2023 / 6 p. : ill https://doi.org/10.48550/arXiv.2303.01816

Hybrid BIST optimization for core-based systems with test pattern broadcastingUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, ZeboDELTA 2004 : second IEEE International Workshop on Electronic Design, Test and Applications : 28-30 January 2004, Perth, Australia : proceedings2004 / p. 3-8 : ill http://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10057

Hybrid BIST time minimization for core-based systems with STUMPS architectureJervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund-Johannes; Jenihhin, Maksim18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings2003 / p. 225-232 : ill

Identification and rejuvenation of NBTI-critical logic paths in nanoscale circuitsJenihhin, Maksim; Squillero, Giovanni; Tihhomirov, Valentin; Kostin, Sergei; Raik, Jaan; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications (JETTA)2016 / p. 273-289 : ill http://dx.doi.org/10.1007/s10836-016-5589-x

Identification and rejuvenation of NBTI-critical paths in nanoscale logic circuitsJenihhin, Maksim1st International Workshop on Reliability and Aging in Forthcoming Electronic Systems : May 28-29, 2015, Cluj-Napoca, Romania2015 / [1] p

Identifying NBTI-critical paths in nanoscale logicUbar, Raimund-Johannes; Vargas, Fabian; Jenihhin, Maksim; Raik, Jaan; Kostin, Sergei; Bolzani Poehls, Leticia16th Euromicro Conference series on Digital System Design : DSD 2013 : proceedings : 4-6 September 2013, Santander, Spain2013 / p. 136-141 : ill

Identifying untestable faults in sequential circuits using test path constraintsViilukas, Taavi; Karputkin, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Fujiwara, HideoJournal of electronic testing : theory and applications (JETTA)2012 / p. 511-521 : ill

Implementation-independent functional test for transition delay faults in microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan2020 23rd Euromicro Conference on Digital System Design (DSD), 26-28 August 2020, Kranj, Slovenia2020 / p. 646-650 https://doi.org/10.1109/DSD51259.2020.00105

Implementation-independent functional test generation for RISC microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]2019 / p. 82-87 : ill https://doi.org/10.1109/VLSI-SoC.2019.8920323

Implementation-independent test generation for a large class of faults in RISC processor modulesJenihhin, Maksim; Oyeniran, Adeboye Stephen; Raik, Jaan; Ubar, Raimund-Johannes24th Euromicro Conference on Digital System Design (DSD)2021 https://doi.org/10.1109/DSD53832.2021.00090

An iterative approach to test time minimization for parallel hybrid BIST architectureUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, Z.5th IEEE Latin-American Test Workshop - LATW 2004 : Cartagena, Colombia, 2004 : digest of papers2004 / p. 98-103 : ill

An iterative approach to test time minimization for parallel hybrid BIST architecturesUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, Z.System-on-Chip Conference 2004 : Bastad, Sweden2004 / p. ?

JÄNES : a NAS framework for ML-based EDA applicationsSelg, Hardi; Jenihhin, Maksim; Ellervee, PeeterIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems2021 https://doi.org/10.1109/DFT52944.2021.9568321

Layout to logic defect analysis for hierarchical test generationJenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Pleskacz, Witold A.; Rakowski, MichalProceedings of the 2007 IEEE Workshop on Design and Diagnostic Circuits and Systems : April 11-13, 2007, Krakow, Poland2007 / p. 35-40 : ill http://dx.doi.org/10.1109/DDECS.2007.4295251

Localization of bugs in processor designs using zamiaCAD frameworkTšepurov, Anton; Tihhomirov, Valentin; Jenihhin, Maksim; Raik, Jaan13th International Workshop on Microprocessor Test and Verification (MTV 2012) Common Challenges and Solutions : Austin, USA, December 10–12, 20122012 / p. 1-6

Measuring and identifying aging-critical paths in FPGAsPfeifer, Petr; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Pliva, ZdenekMEDIAN 2015 : the 4th Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : March 13, 2015, Grenoble, France2015 / p. 56-61 : ill

A methodology for automated mining of compact and accurate assertion setsHeidari Iman, Mohammadreza; Raik, Jaan; Jenihhin, Maksim; Jervan, Gert; Ghasempouri, Tara2021 IEEE Nordic Circuits and Systems Conference (NorCAS) : Oslo, Norway, October 26-272021 / 7 p. : ill https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9599865 https://doi.org/10.1109/NorCAS53631.2021.9599865

Methods to optimize functional safety assessment for automotive integrated circuits = Meetodid autotööstuse kiipide funktsionaalse ohutuse hindamise optimeerimiseksBagbaba, Ahmet Cagri2022 https://doi.org/10.23658/taltech.9/2022 https://digikogu.taltech.ee/et/Item/58b0b89d-b1ba-4a73-ba53-850910d697b5 https://www.ester.ee/record=b5491885*est

Mixed hierarchical-functional fault models for targeting sequential coresRaik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi; Jenihhin, MaksimJournal of systems architecture2008 / 3/4, p. 465-477 : ill

Mixed-level identification of fault redundancy in microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Gürsoy, Cemil Cem; Raik, JaanLATS 2019 : 20th IEEE Latin American Test Symposium : Santiago, Chile,
March 11th - 13th 20192019 / 6 p. : ill https://doi.org/10.1109/LATW.2019.8704591

MLC: a machine learning based checker for soft error detection in embedded processorsNosrati, Nooshin; Jenihhin, Maksim; Navabi, ZainalabedinProceedings - 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design, IOLTS 20222022 / Code 183305 https://doi.org/10.1109/IOLTS56730.2022.9897309 Article at Scopus Article at WOS

Modeling for multi-view interference analysis of design aspects in MPSoC designsVain, Jüri; Apneet Kaur; Tsiopoulos, Leonidas; Raik, Jaan; Jenihhin, MaksimRESCUE 2017 : Workshop on Reliability, Security and Quality : ETS17 Fringe Workshop, May 25-26, 2017, Limassol, Cyprus2017 / p. 1-6 http://www.ets17.org.cy/workshop/rescue-workshop.html

Modeling gate-level abstraction hierarchy using graph convolutional neural networks to predict functional de-rating factorsBalakrishnan, Aneesh; Lange, Thomas; Glorieux, Maximilien; Alexandrescu, Dan; Jenihhin, Maksim2019 NASA/ESA conference on adaptive hardware and systems AHS 2019 : proceedings2019 / p. 72-78 : ill https://doi.org/10.1109/AHS.2019.00007

Modeling microprocessor faults on high-level decision diagrams [Electronic resource]Ubar, Raimund-Johannes; Raik, Jaan; Jutman, Artur; Jenihhin, Maksim; Istenberg, Martin; Wuttke, Heinz-DietrichDSN 2008 : supplemental : 2008 IEEE International Conference on Dependable Systems & Networks With FTCS & DCC (DSN) : June 24-27, 2008, Anchorage, Alaska2008 / p. C17-C22 : ill. [CD-ROM]

Modeling soft-error reliability under variabilityBalakrishnan, Aneesh; Cardoso Medeiros, Guilherme; Gürsoy, Cemil Cem; Hamdioui, Said; Jenihhin, Maksim; Alexandrescu, Dan2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : 6-8 Oct. 20212021 / p. 1-6 https://doi.org/10.1109/DFT52944.2021.9568295

Multi-fragment Markov model guided online test generation for MPSoCVain, Jüri; Tsiopoulos, Leonidas; Kharchenko, Vyacheslav; Apneet Kaur; Jenihhin, Maksim; Raik, JaanICTERI 2017 : ICT in Education, Research and Industrial Applications. Integration, Harmonization and Knowledge Transfer : proceedings of the 13th International Conference on ICT in Education, Research and Industrial Applications. Integration, Harmonization and Knowledge Transfer, Kyiv, Ukraine, May 15-18, 20172017 / p. 594-607 : ill http://www.scopus.com/inward/record.uri?eid=2-s2.0-85020540459&partnerID=40&md5=af226e25c344c52689f23bf5c39cc267 http://ceur-ws.org/Vol-1844/10000594.pdf

Multi-view modeling for MPSoC design aspects [Online resource]Vain, Jüri; Apneet Kaur; Tsiopoulos, Leonidas; Raik, Jaan; Jenihhin, MaksimBEC 2018 : 2018 16th Biennial Baltic Electronics Conference (BEC) : proceedings of the 16th Biennial Baltic Electronics Conference, October 8-10, 20182018 / 4 p.: ill https://doi.org/10.1109/BEC.2018.8600986

Mutation analysis for systemC designs at TLMGuarnieri, Valerio; Bombieri, Nicola; Pravadelli, Graziano; Fummi, Franco; Hantson, Hanno; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes12th IEEE Latin American Test Workshop (LATW) : Porto de Galinhas, Brasil, 27-30 March 20112011 / [6] p

Mutation analysis with high-level decision diagramsHantson, Hanno; Raik, Jaan; Jenihhin, Maksim; Tšepurov, Anton; Ubar, Raimund-Johannes; Guglielmo, Giuseppe di; Fummi, FrancoLATW2010 : 11th Latin-American TestWorkshop, March 28-31, 2010, Punta del Este, Uruguay2010 / [6] p. [CD-ROM]

Nanoelectronics aging mitigation using SSBDD based techniques and dedicated sensorsUbar, Raimund-Johannes; Vargas, Fabian; Jenihhin, Maksim; Raik, JaanMEDIAN Workshop on Circuit Reliability : Modeling and Monitoring, Rome, Italy, February 25, 20132013 / [1] p

New categories of Safe Faults in a processor-based Embedded SystemGürsoy, Cemil Cem; Jenihhin, Maksim; Oyeniran, Adeboye Stephen; Piumatti, Davide; Raik, Jaan; Sonza Reorda, Matteo; Ubar, Raimund-Johannes2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Cluj-Napoca, Romania : proceedings2019 / 4 p. : ill https://doi.org/10.1109/DDECS.2019.8724642

A novel fault-tolerant logic style with self-checking capabilityTaheri, Mahdi; Sheikhpour, Saeideh; Mahani, Ali; Jenihhin, MaksimProceedings - 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design, IOLTS 20222022 / art. 183305 : ill https://doi.org/10.1109/IOLTS56730.2022.9897818

On antagonism between side-channel security and soft-error reliability in BNN inference enginesLai, Xinhui; Lange, Thomas; Balakrishnan, Aneesh; Alexandrescu, Dan; Jenihhin, MaksimIFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)2021 / p. 1-6 https://doi.org/10.1109/VLSI-SoC53125.2021.9606981

On BTI aging rejuvenation in memory address decodersGürsoy, Cemil Cem; Kraak, Daniel; Ahmed, Foisal; Taouil, Mottaqiallah; Jenihhin, Maksim; Hamdioui, Said2022 IEEE 23rd Latin American Test Symposium, LATS 20222022 / Code 184360 https://doi.org/10.1109/LATS57337.2022.9936940

On NBTI-induced aging analysis in IEEE 1687 reconfigurable scan networksDamljanovic, Aleksa; Squillero, Giovanni; Gürsoy, Cemil Cem; Jenihhin, MaksimVLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]2019 / p. 335-340 : ill https://doi.org/10.1109/VLSI-SoC.2019.8920313

On reusability of verification assertions for testingJenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Tšepurov, AntonBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 151-154 : ill

On reusability of verification assertions for testingJenihhin, Maksim; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK kolmanda aastakonverentsi artiklite kogumik : 25.-26. aprill 2008, Voore külalistemaja2008 / p. 43-46 : ill

On test generation for microprocessors for extended class of functional faultsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC: New technology enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 : Revised and Extended Selected Papers2020 / p. 21-44 https://doi.org/10.1007/978-3-030-53273-4 Conference proceedings at Scopus Article at Scopus

On the combined use of HLDDs and EFSMs for functional ATPGDi Guglielmo, Giuseppe; Fummi, Franco; Jenihhin, Maksim; Pravadelli, Graziano; Raik, Jaan; Ubar, Raimund-Johannes5th IEEE East-West Design & Test Symposium EWDTS 2007 : September 7-10, 2007, Yerevan, Armenia2007 / p. 503-508 : ill

On the reuse of TLM mutation analysis at RTLGuarnieri, Valerio; Hantson, Hanno; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications2012 / p. 435-448 : ill

Open-source framework and practical considerations for translating RTL VHDL to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, JaanIP-SoC 2012 : IP Embedded System Conference & Exhibition : Grenoble, France, Dec. 4-5, 20122012

Optimization methodologies for Cycle-Accurate SystemC models converted from RTL VHDLSaif Abrar, Syed; Jenihhin, Maksim; Raik, JaanIP-SoC 2013 : IP embbeded system conference and exhibition : Grenoble, France, November 6-7, 20132013

PASCAL : timing SCA resistant design and verification flowLai, Xinhui; Jenihhin, Maksim; Raik, Jaan; Paul, Kolin2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS 2019) : 1-3 July 2019, Greece2019 / p. 239-242 : ill https://doi.org/10.1109/IOLTS.2019.8854458

Performance analysis of cosimulating processor core in VHDL and SystemCSaif Abrar, Syed; Shyam Kiran A.; Jenihhin, Maksim; Raik, Jaan; Babu, C.Proceedings of the 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI) : 22–25 August 2013, Mysore, India2013 / p. 563-568 : ill

Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 18-20, 2012 Tallinn, Estonia2012 http://www.ester.ee/record=b2777270*est

PSL assertion checkers synthesis with ASM based HLS tool ABELITEJenihhin, Maksim; Baranov, Samary; Raik, Jaan; Tihhomirov, ValentinLATW 2012 : 13th IEEE Latin-American Test Workshop proceedings : April 10th-13th, 2012, Quito, Ecuador2012 / [6 p.] : ill https://ieeexplore.ieee.org/document/6261251

PSL assertion checking using temporally extended high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesJournal of electronic testing : theory and applications2009 / 6, p. 289-300 : ill https://pld.ttu.ee/home/maksim/phd_papers/%5B11%5D%20latw%2708.pdf

PSL assertion checking with temporally extended high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesProceedings of the 9th IEEE Latin-American Test Workshop : LATW2008 : February 17-20, 2008, Puebla, Mexico2008 / p. 49-54 : ill

PSL assertions based verification with HLDD toolsJenihhin, MaksimInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 17-20 : ill

QoSinNoC: analysis of QoS-aware NoC architectures for mixed-criticality applicationsAvramenko, Serhiy; Azad, Siavoosh Payandeh; Niazmand, Behrad; Raik, Jaan; Jenihhin, Maksim21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems : DDECS 2018 : Budapest, Hungary 25-27 April, 2018 : proceedings2018 / p. 67-72 : ill https://doi.org/10.1109/DDECS.2018.00-10

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPGPalermo, N.; Tihhomirov, Valentin; Copetti, Thiago; Jenihhin, Maksim; Raik, Jaan; Kostin, Sergei2015 16th Latin American Test Symposium (LATS 2015) : Puerto Vallarta, Mexico, 25-27 March 20152015 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2015.7102405

Rejuvenation of NBTI-impacted processors using evolutionary generation of assembler programsPellerey, Francesco; Jenihhin, Maksim; Squillero, Giovanni; Raik, Jaan; Sonza Reorda, Matteo; Tihhomirov, Valentin; Ubar, Raimund-Johannes2016 IEEE 25th Asian Test Symposium : 21-24 November 2016, Hiroshima, Japan2016 / p. 304-309 : ill https://doi.org/10.1109/ATS.2016.57

Reliability continuum and academic EDAJenihhin, Maksim2nd International Training School on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN ISTS 2015) : Prague, Czech Republic, July 13-15, 20152015 / [1] p

Representing gate-level SET faults by multiple SEU faults on RT-levelBagbaba, Ahmet Cagri; Jenihhin, Maksim; Ubar, Raimund-Johannes; Sauer, Christian2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 13-15 July 2020 : proceedings2020 / art. 19889351, 6 p. : ill https://doi.org/10.1109/IOLTS50870.2020.9159715

RESCUE : cross-sectoral PhD training concept for interdependent reliability, security and qualityVierhaus, Heinrich Theodor; Jenihhin, Maksim; Sonza Reorda, Matteo2018 12th European Workshop on Microelectronics Education (EWME) : September 24–26, 20182018 / p. 45-50 : ill https://doi.org/10.1109/EWME.2018.8629465

A rescue demonstrator for interdependent aspects of reliability, security and quality towards a complete EDA flowRaik, Jaan; Jenihhin, MaksimProceedings of the 2020 Design, Automation & Test in Europe Conference &Exhibition (DATE 2020), 9 to 13 March, 2020, Grenoble, France2020 / p. 58 https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9116424

RESCUE EDA Toolset for interdependent aspects of reliability, security and quality in nanoelectronic systems designGürsoy, Cemil Cem; Cardoso Medeiros, Guilherme; Chen, Juanho; Balakrishnan, Aneesh; Lai, Xinhui; Bagbaba, Ahmet Cagri; Raik, Jaan; Jenihhin, MaksimDATE 20192019 / 1 p. : ill https://doi.org/10.5281/zenodo.3362529 https://past.date-conference.com/

RESCUE: interdependent challenges of reliability, security and quality in nanoelectronic systemsJenihhin, Maksim; Raik, Jaan2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 9-13 March 2020, Grenoble, France : proceedings2020 / art. 19690741 , 6 p https://doi.org/10.23919/DATE48585.2020.9116558

Sequential circuits BIST synthesis from signal specificationsRaik, Jaan; Jenihhin, Maksim; Adelbert, RainProceedings 23rd NORCHIP Conference : Oulu, Finland, 21-22 November 20052005 / p. 196-199 : ill

Simulation-based hardware verification with high-level decision diagrams = Simuleerimisel põhinev riistvara verifitseerimine kõrgtaseme otsustusdiagrammidelJenihhin, Maksim2008 https://www.ester.ee/record=b2431332*est

Simulation-based verification with APRICOT framework using high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesEast-West Design & Test Symposium : Moscow, September 18-21, 20092009 / p. 13-16 : ill

Software-based mitigation for memory address decoder agingKraak, D. H. P.; Gürsoy, Cemil Cem; Jenihhin, Maksim; Raik, JaanLATS 2019 : 20th IEEE Latin American Test Symposium : Santiago, Chile, March 11th - 13th 20192019 / 6 p. : ill https://doi.org/10.1109/LATW.2019.8704595

Software-level TMR approach for on-board data processing in space applicationsJanson, Karl; Treudler, Carl Johann; Hollstein, Thomas; Raik, Jaan; Jenihhin, Maksim; Fey, Goerschwin21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems : DDECS 2018 : Budapest, Hungary 25-27 April, 2018 : proceedings2018 / p. 147-152 : ill https://doi.org/10.1109/DDECS.2018.00033

Special session : AutoSoC - a suite of open-source automotive SoC benchmarksSilva, Felipe Augusto da; Bagbaba, Ahmet Cagri; Ruospo, Annachiara; Jenihhin, Maksim2020 IEEE 38th VLSI TEST SYMPOSIUM (VTS) - VTS 2020 : proceedings2020 / 9 p. : ill https://doi.org/10.1109/VTS48691.2020.9107599 Conference Proceedings at Scopus Article at Scopus Article at WOS

SPICE-inspired fast gate-level computation of NBTI-induced delays in nanoscale logicKostin, Sergei; Raik, Jaan; Ubar, Raimund-Johannes; Jenihhin, Maksim2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings2015 / p. 223-228 : ill

A survey on UAV computing platforms : a hardware reliability perspectiveAhmed, Foisal; Jenihhin, MaksimSensors2022 / art. 6286 https://doi.org/10.3390/s22166286 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

A synthetic, hierarchical approach for modelling and managing complex systems' quality and reliability = Sünteetiline, hierarhiline lähenemine keerukate süsteemide kvaliteedi ja töökindluse modelleerimiseks ja haldamiseksBalakrishnan, Aneesh2022 https://doi.org/10.23658/taltech.11/2022 https://digikogu.taltech.ee/et/Item/a594d3ec-0e6b-4a78-819a-fe1f47992612

SystemC-based loose models : RTL abstraction for design understandingAbrar, Syed Saif; Jenihhin, Maksim; Raik, JaanWorkshop on Design Automation for Understanding Hardware Designs DUHDe 2015 : Grenoble, March 13, 20152015 / p. 1-6

SystemC-based loose models for simulation speed-up by abstraction of RTL IP coresAbrar, Syed Saif; Jenihhin, Maksim; Raik, Jaan2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings2015 / p. 71-74 : ill http://dx.doi.org/10.1109/DDECS.2015.39

zamiaCAD : open source platform for advanced hardware designTšepurov, Anton; Jenihhin, Maksim; Raik, JaanDATE 2011 University Booth : Design Automation and Test in Europe : Grenoble, France, March 14-18, 20112011 / [2] p.: ill

zamiaCAD : shall we dance?Jenihhin, MaksimOpen Source Tools for Verification : DVClub 14 January 20132013 / 1 p

zamiaCAD : understand, develop and debug hardware designsJenihhin, Maksim; Tihhomirov, Valentin; Saif Abrar, Syed; Raik, Jaan; Bartsch, GünterDUHDe : 1st Workshop on Design Automation for Understanding Hardware Designs : March 28, 2014 : Friday Workshop at DATE 2014, Dresden, Germany2014 / p. 1-6

Temporally extended high-level decision diagrams for PSL assertions simulationJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesProceedings : Thirteenth IEEE European Test Symposium : ETS 2008 : 25-29 May 2008, Verbania, Italy2008 / p. 61-68 : ill

Test time minimization for hybrid BIST of core-based systemsJervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund-Johannes; Jenihhin, Maksim12th Asian Test Symposium (ATS 2003) : 17-19 November 2003, Xian, China2003 / p. 318-325 : ill

Test time minimization for hybrid BIST of core-based systemsJervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund-Johannes; Jenihhin, MaksimJournal of computer science and technology2006 / 6, p. 907-912 : ill https://link.springer.com/article/10.1007/s11390-006-0907-x

Test time minimization for hybrid BIST with test pattern broadcastingUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, ZeboIEEE NORCHIP 2003 : 21 Norchip Conference : Riga, Latvia, 10-11 November 2003 : proceedings2003 / p. 112-116 : ill

The validation of graph model-based, gate level low-dimensional feature data for machine learning applicationsBalakrishnan, Aneesh; Lange, Thomas; Glorieux, Maximilien; Alexandrescu, Dan; Jenihhin, Maksim2019 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC), 29-30 October 2019, Helsinki, Finland : proceedings in IEEE Xplore2019 / 7 p https://doi.org/10.1109/NORCHIP.2019.8906974

Timing-critical path analysis with structurally synthesized BDDsUbar, Raimund-Johannes; Jürimägi, Lembit; Jenihhin, Maksim; Raik, Jaan; Olugbenga, Niyi-Leigh; Viies, Vladimir2018 7th Mediterranean Conference on Embedded Computing (MECO)2018 / 6 p. : ill https://doi.org/10.1109/MECO.2018.8406051

Towards multidimensional verification : where functional meets non-functionalJenihhin, Maksim; Lai, Xinhui; Ghasempouri, Tara; Raik, Jaan2018 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC) : 30-31 October 2018, Tallinn, Estonia : proceedings in IEEE Xplore2018 / 7 p. : ill https://doi.org/10.1109/NORCHIP.2018.8573495

True path tracing in structurally synthesized BDDs for testability analysis of
digital circuitsUbar, Raimund-Johannes; Jürimägi, Lembit; Oyeniran, Adeboye Stephen; Jenihhin, MaksimEuromicro Conference on Digital System Design : DSD 2019 : 28 - 30 August 2019
Kallithea, Chalkidiki, Greece : proceedings2019 / p. 492-499 : ill https://doi.org/10.1109/DSD.2019.00077

TTBist: a DfT tool for enhancing functional test for SoCHermann, K.; Raik, Jaan; Jenihhin, MaksimBEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference2006 / p. 191-194 : ill

2018 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC) : 30-31 October 2018, Tallinn, Estonia : proceedings in IEEE Xplore [Online resource]2018 https://ieeexplore.ieee.org/xpl/conhome/8552599/proceeding

Tööstusdoktorantuur projektis RESCUEJenihhin, MaksimMente et Manu2017 / lk. 21 http://www.ester.ee/record=b1242496*est

Understanding multidimensional verification : where functional meets non-functionalLai, Xinhui; Balakrishnan, Aneesh; Lange, Thomas; Jenihhin, Maksim; Ghasempouri, Tara; Raik, Jaan; Alexandrescu, DanMicroprocessors and microsystems2019 / art. 102867, 13 p. : ill https://doi.org/10.1016/j.micpro.2019.102867 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

Universal mitigation of NBTI-induced aging by design randomizationJenihhin, Maksim; Kamkin, Alexander; Navabi, Zainalabedin; Sadeghi-Kohan, SomayehProceedings of 2016 IEEE East-West Design & Test Symposium (EWDTS) : Yerevan, Armenia, October 14-17, 20162017 / [5] p. : ill http://dx.doi.org/10.1109/EWDTS.2016.7807635

Unsupervised recycled FPGA detection using symmetry analysisTarique, Tanvir Ahmad; Ahmed, Foisal; Jenihhin, Maksim; Ali, Liakot12th International Conference on Electrical and Computer Engineering : ICECE 20222022 / p. 437-440 https://doi.org/10.1109/ICECE57408.2022.10088856

Upgrading QoSinNoC : efficient routing for mixed-criticality applications and power analysisAvramenko, Serhiy; Azad, Siavoosh Payandeh; Violante, Massimo; Niazmand, Behrad; Raik, Jaan; Jenihhin, MaksimProceedings of the 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) : October 8-10, 2018, Verona, Italy2018 / p. 207-212 : ill https://doi.org/10.1109/VLSI-SoC.2018.8644866

Using simulation statistics for bug localization in RTL designsTihhomirov, Valentin; Jenihhin, Maksim; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK seitsmenda aastakonverentsi artiklite kogumik : 15.-16. novembril 2013, Haapsalu2013 / p. 107-110 : ill

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VHDL design debug framework based on zamiaCADTihhomirov, Valentin; Tšepurov, Anton; Saif Abrar, Syed; Jenihhin, Maksim; Raik, JaanDATE 2013 : Design Automation and Test in Europe, March 18-22, 2013, Grenoble, France2013 / [1] p. : ill