A global methodology for test program generation starting from high level specificationsStorojev, Sergei; Leveugle, Regis; Saucier, GabrieleBEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia). 11994 / p. 305-311: ill

Automatic circuit partitioning for FPGAsKrupnova, Helena; Abbara, A.; Brasen, D.; Saucier, GabrieleBEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 389-392: ill

Circuit partitioning method for FPGAsKrupnova, Helena; Saucier, GabrieleProceedings of the Estonian Academy of Sciences. Engineering1997 / 4, p. 283-292

Compaction of decision diagrams for describing multi-process VHDL descriptionsLeveugle, R.; Saucier, Gabriele; Ubar, Raimund-JohannesBEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 195-198: ill

Management system for electronic virtual componentsSaucier, GabrieleBEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 1-6: ill

Methode et outil de prototypage des systemes integres sur FPGAs : [doktoriväitekiri]Krupnova, Helena1999

User-guided hierarchical FPGA partitioningKrupnova, Helena; Saucier, GabrieleBEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 187-190: ill