Defect oriented fault coverage of 100stuck-at fault test setsBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 7th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2000 : Gdynia, Poland, 15-17 June 20002000 / p. 511-516 : ill

Defect-oriented fault simulation and test generation in digital circuitsKuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE ISQED 2001 : proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design : March 26-28, 2001, San Jose, California2001 / p. 365-371

Defect-oriented library builder and hierarchical test generationCibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS 2001 : Fourth International Workshop on IEEE Design and Diagnostics of Electronic Circuits and Systems : Györ, Hungary, April 18-20, 20012001 / p. 163-168 : ill

Defect-oriented test generation and fault simulation in the environment of MOSCITOSchneider, Andre; Diener, Karl-Heinz; Gramatova, Elena; Fisherova, Maria; Ivask, Eero; Ubar, Raimund-Johannes; Pleskacz, Witold A.; Kuzmicz, W.BEC 2002 : proceedings of the 8th Biennial Baltic Electronics Conference : October 6-9, 2002, Tallinn, Estonia2002 / p. 303-306 : ill

Defect-oriented test generation using probabilistic estimationCibakova, Tatiana; Fischerova, Maria; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 8th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2001 : Zakopane, Poland, 21-23 June 20002001 / p. 131-136 : ill

Hierarchical defect level test quality analysisBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesVILAB User Forum2000 / [11] p

Hierarchical defect-oriented fault simulation for digital circuitsBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE European Test Workshop : 23-26 May 2000, Cascais, Portugal : ETW 2000 : proceedings2000 / p. 69-74 : ill

Hierarchical defect-oriented fault simulation for digital circuitsBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE European Test Workshop2000 / p. 151-156 https://ieeexplore.ieee.org/document/873781

Hierarchical test generation for combinational circuits with real defects coverageCibakova, Tatiana; Fischerova, Maria; Gramatova, Elena; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesMicroelectronics reliability2002 / p. 1141-1149 : ill

Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvementBlyzniuk, M.; Kazymyra, I.; Kuzmicz, W.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesMicroelectronics reliability2001 / p. 2023-2040 : ill

Virtual laboratory for research in dependable microelectronicsDiener, Karl-Heinz; Elst, G.; Gramatova, Elena; Kuzmicz, W.; Peng, Z.; Ubar, Raimund-JohannesThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 217-220 : ill