An approach for verification assertions reuse 2 in RTL test pattern generationJenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi; Fujiwara, HideoJournal of Shanghai Normal University : Natural Sciences2010 / p. 441-447 : ill https://www.researchgate.net/publication/240613999_An_Approach_for_Verification_Assertions_Reuse_in_RTL_Test_Pattern_Generation

An approach for verification assertions reuse in RTL test pattern generationJenihhin, Maksim; Raik, Jaan; Fujiwara, Hideo; Ubar, Raimund-Johannes; Viilukas, TaaviDigest of papers : IEEE 11th Workshop on RTL and High Level Testing : WRTLT'10 : December 5-6, 2010, Shanghai, China2010 / p. 107-110 : ill

Constraint-based hierarchical untestability identification for synchronous sequential circuitsRaik, Jaan; Rannaste, Anna; Jenihhin, Maksim; Viilukas, Taavi; Ubar, Raimund-Johannes; Fujiwara, HideoSixteenth IEEE European Test Symposium : 23-27 May 2011, Trondheim2011 / p. 147-152

Constraint-based hierarchical untestability identification for syncronous sequential circuitsViilukas, Taavi; Raik, Jaan; Ubar, Raimund-Johannes; Rannaste, Anna; Jenihhin, Maksim; Fujiwara, HideoInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK viienda aastakonverentsi artiklite kogumik : 25.-26. novembril 2011, Nelijärve2011 / p. 139-142 : ill

Identifying untestable faults in sequential circuits using test path constraintsViilukas, Taavi; Karputkin, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Fujiwara, HideoJournal of electronic testing : theory and applications (JETTA)2012 / p. 511-521 : ill

RT-level identification of potentially testable initialization faultsRaik, Jaan; Fujiwara, Hideo; Krivenko, AnnaThe Ninth IEEE Workshop on RTL and High Level Testing (WRTLT 2008), Sapporo, Japan2008 / [6] p

Untestable fault identification in sequential circuits using model-checkingRaik, Jaan; Fujiwara, Hideo; Ubar, Raimund-Johannes; Krivenko, AnnaProceedings of the 17th Asian Test Symposium ATS 2008 : November 24-27, 2008, Sapporo, Japan2008 / p. 21-26 : ill http://dx.doi.org/10.1109/ATS.2008.22

Untestable fault identification in sequential circuits using model-checkingRaik, Jaan; Fujiwara, Hideo; Ubar, Raimund-Johannes; Krivenko, Anna2002-2011 : 20th Anniversary compendium of papers from Asian Test Symposium2011 / p. 257-262 : ill https://ieeexplore.ieee.org/document/4711554